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    In this last part in our series of lectures
    on computer organization, let us take a look
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    at the bus.
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    What is a bus?
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    So far we had seen the blocks of CPU, memory,
    I/O and the interconnecting bus.
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    On more than one occasion, I had pointed out
    that we have to evolve some kind of standardization
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    so that the system from the bus we will see
    something uniform because you may be having
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    different types of memory systems and you
    may be having different types of devices but
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    the CPU must see something uniform on the
    bus on the bus end.
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    In spite of all these, though we talk about
    standards, we would find that there are different
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    standards; obviously because the CPU and memory
    work at some rate different from I/O.
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    If at all CPU is directly involved, that is
    going to be at another rate; then, memory
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    I/O will be a different rate; and in I/O,
    you have a spectrum from the lowest K speed
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    to the fastest one.
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    So generally, we would find that there are
    different types of buses and when a processor
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    comes with some brand name in the market,
    you would find that that particular manufacturer
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    comes out with its own bus also.
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    By the time that particular bus gets standardized,
    you would find that the bus is no longer very
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    relevant, mainly because the processor is
    outdated.
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    Nevertheless, we can always talk in the case
    of bus; in general, about the specifications
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    of the bus.
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    Here there are certain things which you may
    find are common and there are certain things
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    which would keep varying.
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    Now while specifying a bus, what exactly is
    the bus; what is it we have talked about earlier?
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    We have always said a bus is a set of signal
    lines.
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    We had introduced the bus as a set of signal
    lines.
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    Bus in fact is a term introduced by Americans;
    earlier the British used to call it highway.
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    Now that particular term is coming in a different
    context like super highway for information
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    and so on.
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    Earlier they were calling it highway.
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    Essentially on a highway something moves;
    but Americans used the bus.
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    Now in the case of computer system, we can
    say the bus is like a highway over which the
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    data moves – there is some communication.
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    But Americans called it bus – since bus
    is a set of signal lines, these signal lines
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    are carried over lines, which form conductors.
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    So the bus has conductors and a bus is usually
    long; while trying to meet an electrical specification,
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    you will find that you would need some current
    amplifiers, we call them current drivers.
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    That means along with the bus or as part of
    a bus, you have drivers.
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    So you can see that a bus has drivers and
    conductors and we are quite familiar with
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    the term bus.
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    Now let us go into certain aspects of the
    specifications.
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    There are actually three types of specifications
    but usually in computer organization, or we
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    may say even computer scientists will be concerned
    more with only one thing.
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    That particular thing is called the logical
    specification of the bus.
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    In fact all the time when we were talking
    about some transfer over the bus, we were
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    indicating this.
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    What is it we said earlier?
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    We said the CPU places address on the bus
    and if it were a read cycle, the CPU also
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    places a read signal on the bus, and then
    the memory responds with data and it puts
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    it on the bus.
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    CPU, of course, reads it in.
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    So you can see that there is generation of
    address, signal generation of read signal
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    and strobing the data that’s available.
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    This is what we were talking about all the
    time.
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    Now what is the data?
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    Data is a pattern of 1s and 0s; it is a string
    of 1s and 0s.
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    Similarly address also is a string.
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    So all the time we were only talking about
    the logical aspect of it because we never
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    said the data which is 1 means say 1 volt;
    0 means say 0 volts or any such thing; we
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    did not talk about any physical, real-world
    quantity.
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    We were not referring to any physical quantity.
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    We are talking about a read as a read signal,
    write as a write signal.
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    We never said read means what must be the
    voltage and so on and so forth.
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    So that is what we are talking about when
    we talk about the logical specification; another
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    thing as you would have noticed is that we
    are talking about sequence of actions.
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    What are the things we were mentioning?
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    We said first address, then read and then
    the data comes, which is strobed, so we were
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    talking about sequence also.
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    In other words, the sequence of actions which
    is part of what we refer to as bus protocol,
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    is only one specific way in which this read
    or write can be performed.
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    So we talk about logical signals involved
    and then we also talk about the sequence in
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    which the signals must be generated.
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    Now generally when we discuss the bus in computer
    science, or from a computer scientist’s
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    point of view, we will always be concerned
    with these logical aspects.
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    But later as I was just trying to point out,
    there are two things: one is the electrical
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    specification.
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    So when we talk about the electrical specification
    of the bus, I have to say for instance what
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    does 1 mean?
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    Do 1 and 0 there refer to say some voltage
    signals or current signals or some other signals?
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    And if for instance 1 and 0 will be represented
    by plus 5 V and 0 V or 3 V, plus 3 V and plus
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    0.2 V or let us say plus 15 V and minus 15
    V.
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    All these things really refer to the physical
    quantities.
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    They would come into the electrical specification
    of the bus.
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    It is not enough if we say that the address
    is placed.
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    We have to specify exactly what must be the
    levels of the voltage or current signals.
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    Essentially we can just put it as physical
    specification, but then the mechanical specification
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    of the bus also has to be specified.
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    So together, these two form the physical part
    of the bus and this forms the logical part
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    of the bus.
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    One talks about the electrical signal levels
    and so on, the other one talks about the mechanical
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    thing.
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    So this would say how long the bus conductor
    can be and what sort of edge connector is
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    used – is it something like 32 pin or 62
    pin and if it is this pin, is it a parallel
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    or are the pins parallel or staggered, etc.
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    For instance, if we talk about the standard
    bus, we have specification along all the three
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    dimensions.
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    If we say multi-bus, there is a specific multi-bus
    connector and each of the multi-bus signals
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    is going to be defined in terms of some electrical
    voltage current and so on.
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    And then we also talk about this particular
    one.
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    So essentially we will only concentrate on
    this.
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    But let us not forget that there are these
    specifications also; somebody must concern
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    with this; otherwise there is no standard.
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    Now why must we be concerned even down to
    the level of mechanical?
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    That is mainly because this is the one which
    is going to give freedom to the user.
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    So if we say use multi-bus one connector or
    multi-bus two connectors or some other X bus,
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    new bus, and then all he does is he goes to
    the shop and ask for that connector and then
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    brings it and then machine properly without
    any difficulty.
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    He is not going to be bothered about either
    logical aspect or electrical aspect; for him,
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    when he keys in, there must be a display and
    that particular display must mean something
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    to him at a higher level.
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    Having said that, we will be concentrating
    on the logical aspects of this bus.
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    We can note that essentially there are again
    three sections.
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    The first one we may say is concerned with
    the data transfer.
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    This is the one we keep talking all that time
    about.
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    That is, we say that the CPU places address,
    indicates what type of transfer, read or write,
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    input or output, whatever it wants, and then
    memory or I/O responds.
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    So all these things: placing the address,
    placing the appropriate control signal, and
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    then passing on the data will come under the
    data transfer aspect.
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    Now as the CPU is involved in this data transfer
    because what is going on in any instruction
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    cycle again and again is the same thing, fetching
    an instruction, interpreting, executing, as
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    part of executing fetching a data, that is,
    instruction or data fetching – it all comes
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    under the data transfer.
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    This is what is going on in every instruction
    cycle.
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    Now this is the essential thing as far as
    the processor is concerned.
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    As this goes on some other device may indicate
    that it is ready; in the case of interrupt,
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    is it not.
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    Now in a system which has n number of devices,
    that is, multiple devices, we also said that
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    we have to look in to the priority among these
    when there is a multiple request for this
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    CPU attention.
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    So we have to basically see that there is
    priority checking and so on.
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    We may put this particular one as priority
    arbitration; meaning as CPU is busy with the
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    transfer, then possibly there is some other
    specialized hardware unit, which looks into
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    the action.
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    Priority arbitration can go on in parallel
    with the data transfer.
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    For instance as part of the some instruction
    cycle, when one of the n devices or two of
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    the devices indicate that readiness, then
    there is a conflict.
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    Now the priority arbitrator will look in to
    the requests and then will choose the higher
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    priority device between those two so that
    when the instruction cycle is complete it
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    can go ahead, that is, in the case of interrupt.
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    So priority arbitration is another piece of
    action that goes on and we will have dedicated
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    signal lines as part of the bus because then
    only two things can go on in parallel; otherwise
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    it is not possible.
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    If the same sets of signal lines are going
    to be used, one has to keep idling.
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    For instance that was the situation in the
    case of DMA.
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    The I/O is directly accessing the memory so
    CPU is going out of action.
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    The third aspect of this bus we may just put
    in general as initialization.
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    Different people may call it differently.
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    What exactly we mean here is something to
    do with checking about the power, the system
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    clock, and few other signal lines, which really
    not take direct part in data transfer or priority
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    arbitration.
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    There will be another set of signal lines.
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    We may just call them for instance system
    reset signal.
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    So that can come under the initialization
    and a few other things: system clock, system
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    reset, some special signal lines, monitoring
    the power – all these things will come under
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    this.
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    So we as we talk about the data transfer;
    we should also take a look at what is going
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    on in this and also know the functions of
    some of these because there is no standard
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    about this particular thing.
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    So generally when you study any bus, you may
    be able to identify a group of signals belonging
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    to this or this or this category.
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    Now there are different types of buses, we
    may say.
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    Actually I am not talking about just the standard
    buses here.
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    I am just trying to give what you may call
    a generic or general classification.
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    What are the various things involved?
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    For instance, we are not talking about multi-bus
    or a new bus or uni-bus or a mass bus and
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    so on; we are discussing purely from functional
    point of view.
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    Now we know that CPU and memory, both work
    at electronic speed.
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    So it is meaningful to have a processor memory
    bus and have it somewhat different, distinct
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    from what you may call the second one as an
    I/O bus mainly because in the case of processor
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    memory, the transfer is going to be very fast
    whereas in the case of I/O bus, we do not
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    know.
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    We have devices with varying speeds, characteristics,
    and what not.
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    Then there is another bus also that we talk
    about; that is generally called a back plane
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    bus.
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    In some systems we may not able to identify
    them separately.
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    For instance the processor of the memory bus
    itself may act as a back plate bus; it is
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    not necessary that all the three must exist
    in all the systems.
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    Now let us say some one is looking up the
    system with an Intel processor.
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    Then suited with that particular Intel processor,
    there may be certain memory chips.
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    It is even possible that the manufacturer
    of the processor or the CPU has also come
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    up with a set of memory chips, which would
    directly talk in the sense there will be some
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    special features about that memory.
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    For instance let us say suppose you have a
    processor with multiplexed bus, there is let
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    us say address and data multiplex.
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    If you have the memory chips or the memory
    controller, which goes with the chip in the
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    memory bus system, it can take care of the
    multiplexing, so that internally it buffers
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    and then de-multiplexes that.
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    Then it is meaningful; and so what happens
    is this processor memory bus essentially we
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    may say is a short bus and also it is a bus
    which does transaction as fast as possible.
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    We can understand fast because, for this processor
    utilization to be the highest, maximal, it
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    must be fast and invariably the processor,
    memory, and the bus are interconnecting the
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    processor memory bus on a single board itself.
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    That is why invariably we define that particular
    thing as a short bus and there may not be
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    any standard about this also.
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    For an Intel processor, there may be a set
    of things; for a Motorola processor there
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    may be another set of things.
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    It is all because of the signals that are
    generated by the respective processor.
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    We can say that this processor memory bus
    is a proprietary bus because we have a specific
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    processor and then we have specific memory
    requirement; it is not open for the general
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    use.
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    Now in the case of I/O bus, it is a different
    story.
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    First of all, we have different types of devices
    to be connected; and second thing is that
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    whereas in the case of processor memory even
    at the time of the design it is known how
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    much of memory it has, at the time of the
    system installation, we do not know how many
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    devices we want – may be during installation
    we would like to add a few more devices.
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    Generally we would find this I/O bus is in
    contrast with the other one.
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    I/O bus will be a long and slow bus; slow
    because essentially it is concerned with the
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    I/O part.
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    Generally it is lower compared with the other
    one, which is the processor memory bus, and
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    it is also a long bus because you may have
    to have many connectors for the expansion
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    of these devices and so on.
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    So we have a range of speeds to be taken care
    of in the I/O; it is more or less standardized
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    in the processor memory.
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    The user is not directly concerned with this
    whereas the user is very much concerned with
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    this.
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    And the third one, the back plane bus, is
    on the PC board itself.
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    You have the set of signal lines connected
    that is why it has derived the name back plane.
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    As I said in some systems the back plane bus
    itself may be the processor memory bus.
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    So through a few system configurations we
    will just see the essential difference between
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    these back plane buses.
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    But we take it as the back plane bus is one
    in which you have the entire set of signal
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    lines on the PCB itself; so that is how it
    got the name back plane.
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    Now regarding the requirements, it so happens
    that there are two requirements for a bus
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    and they seem to be also conflicting.
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    We generally talk about bus latency.
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    What is the bus latency?
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    Whenever there is a requirement of the bus
    for a data transfer, you would like to see
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    that the bus is made available as fast as
    possible for the specific requirement.
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    So we would have to see that the bus latency
    time must be minimized.
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    The time associated with the bus latency must
    be minimized; that is, whenever there is a
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    request for the bus, the bus must be made
    available with the least delay possible.
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    Then the other factor is the bus bandwidth.
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    This particular one conveys to us that if
    the bandwidth is high, more data can be transferred;
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    that is, there is more efficient utilization.
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    Now more data can be transferred
    if we can bunch all the data, buffer it and
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    then send it with the least amount of interaction
    asking for address, control, things like that.
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    As we have seen for instance in the DMA, the
    data is ready and available and then, like
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    a machine gun, it keeps going.
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    Every time we do not have to keep checking.
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    So the bus bandwidth can be increased by what
    we say as buffering the data and transmitting
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    block of data so that the time that is generally
    lost between two blocks or pieces of data
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    can be further minimized.
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    So there is buffering or storing more data
    before the actual transmission starts.
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    So what we exactly gain here is that before
    the transmission, there may be some overheads
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    and delay, but then there should not be any
    delay once the transmission starts, and once
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    it starts, it goes very fast.
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    While buffering a block and transmitting blocks
    of data, you maximize the bandwidth.
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    Now what happens?
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    When there is a block data transfer, the bus
    is not going to be available for some other
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    device which requires it.
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    That is because when the bus is being used
    by some other device, the one which requires
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    the bus is going to wait; that is the reason.
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    Now as we said the latency must be minimized;
    that is, the wait period must be minimized.
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    We also say that the bus bandwidth must be
    maximized.
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    Now while trying to maximize this, we ended
    up buffering the data and then transmitting
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    the blocks of data; and while trying to maximize
    this, we see that the latency gets affected.
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    That is, the device which requests the bus
    has to wait because some other large transfer
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    is going on.
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    So these two – bus latency and bus bandwidth
    – are actually conflicting requirements,
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    so there must be some compromise between these;
    now this is very important.
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    Talking about different types of buses from
    the timing point of view we talk about synchronous
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    buses in which the transmission takes place.
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    It is synchronized with some clock and of
    course the asynchronous bus.
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    We have both types of buses; generally you
    will find that when synchronous bus is used
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    everything must be known a priori.
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    For instance, in the case of processor–memory
    interaction, the speed of the processor and
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    how exactly memory is organized is known,
    whereas when it comes to I/O device we were
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    not sure.
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    We may add slow device and fast device later
    on also; a priori we will not have everything.
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    So it may be better to say that it depends
    on the individual characteristic of the device.
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    The bus transmission must be flexible; for
    this asynchronous is better.
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    If everything is known a priori, then we can
    make those elements in synchronous, or rather
  • 29:46 - 29:48
    work in synchronous.
  • 29:48 - 29:58
    That is, for instance, we have talked about
    synchronous action earlier.
  • 29:58 - 30:12
    Remember in the initial period we are talking
    about the states and in each state we were
  • 30:12 - 30:15
    saying some minimum action was going on.
  • 30:15 - 30:22
    The minimum action is going on and then the
    state itself is being defined by the clock
  • 30:22 - 30:24
    of the system.
  • 30:24 - 30:28
    That is in connection with CPU, we are talking
    about it.
  • 30:28 - 30:38
    Remember then we were saying in state T1 the
    address is placed; let us say the address
  • 30:38 - 30:41
    line may be either 1 or 0.
  • 30:41 - 30:50
    So either it may be this way or it may this
    way; actually this particular one refers to
  • 30:50 - 30:55
    rise time and fall time.
  • 30:55 - 31:07
    So in T1 the addresses is placed on the bus
    and, let us say, in T2 the read control signal
  • 31:07 - 31:11
    is generated.
  • 31:11 - 31:14
    The read control signal is generated in T2.
  • 31:14 - 31:19
    The address has been placed; the read control
    signal is generated; let us say that particular
  • 31:19 - 31:23
    going signal is 0 to 1.
  • 31:23 - 31:32
    That is, T1 address is placed; T2 wait control
    signal is generated; on seeing read, the memory
  • 31:32 - 31:39
    responds with the data from the location indicated
    by the address.
  • 31:39 - 31:43
    So from now from the memory side this is all
    this from the CPU side.
  • 31:43 - 31:52
    Now to indicate that the memory is different
    from these we will call these as the data
  • 31:52 - 31:55
    coming from the memory or memory dot data.
  • 31:55 - 32:08
    The data that is coming some time after the
    memory sees the control signal read.
  • 32:08 - 32:13
    So let us say there is some delay.
  • 32:13 - 32:17
    I am just indicating the delay by this delta.
  • 32:17 - 32:23
    There is some delay from the time the control
    signal is generated to the time the data is
  • 32:23 - 32:25
    generated.
  • 32:25 - 32:33
    This data actually refers to the data being
    0.
  • 32:33 - 32:39
    We do not know; may be some bit is 0, some
    bit is 1, so we would represent both.
  • 32:39 - 32:44
    For instance if the memory responds to the
    8-bit data, some bits will be 1; some bits
  • 32:44 - 32:47
    will be 0.
  • 32:47 - 32:52
    Some bits may continue to be 1; some bits
    may continue to be 0.
  • 32:52 - 33:03
    So when we mark this way, it basically means
    it can be 1 or 0; this delta is the delay.
  • 33:03 - 33:11
    This delay is due to the memory responding
    to the control signal read.
  • 33:11 - 33:20
    There can also be delay introduced by the
    memory – that is when we talk about reading
  • 33:20 - 33:25
    the data; delay with reference to the address
    also is possible.
  • 33:25 - 33:29
    It is not shown here; here only the particular
    delay is shown.
  • 33:29 - 33:42
    Now here you can see that assuming this delta,
    the delay, is less than one clock period,
  • 33:42 - 33:50
    then we say that before T3 comes, this data
    can be read.
  • 33:50 - 33:54
    This indicates that the read control signal
    in this says data is available.
  • 33:54 - 33:59
    That is, we may refer to this as valid data.
  • 33:59 - 34:08
    We say valid data because before this instant,
    the data was not valid; during this instant,
  • 34:08 - 34:11
    there is some transition.
  • 34:11 - 34:13
    Now the valid data is available.
  • 34:13 - 34:20
    The CPU can actually read any time after this
    and even before T3.
  • 34:20 - 34:32
    In this duration, the CPU can strobe it in,
    but if you want to be very careful you can
  • 34:32 - 34:38
    see that at T3 this information is strobed,
    meaning, let us say something like this.
  • 34:38 - 34:46
    For the read control this edge is used; this
    edge is used for reading.
  • 34:46 - 34:53
    If that is so, we say that reading of the
    data is synchronized with the clock.
  • 34:53 - 35:02
    Here this is a clear picture of synchronous
    transmission, synchronizing with the T1 clock,
  • 35:02 - 35:09
    the address is generated; synchronizing with
    T2 clock, read control is generated; and in
  • 35:09 - 35:17
    response to the read control, the memory places
    the data on the bus and synchronizing with
  • 35:17 - 35:23
    T3, the data is read by the CPU.
  • 35:23 - 35:31
    So this is the synchronized transmission,
    which means we know for sure that this delta
  • 35:31 - 35:36
    is not going to be more than this period.
  • 35:36 - 35:39
    That is, well before T3, the valid data is
    available.
  • 35:39 - 35:45
    In case this is not available, we had talked
    about the situation earlier.
  • 35:45 - 35:53
    In case before the next clock pulse the valid
    data is not available, that means memory is
  • 35:53 - 35:58
    not responding to this control and address
    signals.
  • 35:58 - 36:00
    It needs more time.
  • 36:00 - 36:11
    We assume this particular period is 100 nanoseconds
    and the memory is delaying let us say by 150
  • 36:11 - 36:12
    nanoseconds.
  • 36:12 - 36:16
    That is, only 50 nanoseconds later, the valid
    data will be available, which means well before
  • 36:16 - 36:27
    the next pulse, that is, T4, the data will
    be available.
  • 36:27 - 36:32
    So reading cannot be performed here; so what
    will be done?
  • 36:32 - 36:40
    What can be done is the read control signal
    must be further extended beyond and taken
  • 36:40 - 36:49
    up to T4 because the data is not going to
    be available here.
  • 36:49 - 36:54
    It is going to be available somewhere about
    50 nanoseconds later.
  • 36:54 - 37:07
    So the actual valid data will be available
    here itself; that means 1 clock pulse later,
  • 37:07 - 37:13
    that data can be read.
  • 37:13 - 37:17
    How is this achieved?
  • 37:17 - 37:23
    The extension of this read pulse and delaying
    the reading is achieved as we had seen earlier.
  • 37:23 - 37:35
    We said that the CPU can have a ready input,
    which can be used by the memory subsystem,
  • 37:35 - 37:48
    and as soon as the memory system sees the
    read pulse, it can immediately say that the
  • 37:48 - 37:57
    CPU, rather memory, is not ready.
  • 37:57 - 38:08
    Now on seeing this ready input to the CPU,
    on seeing that memory is not ready, then until
  • 38:08 - 38:18
    it becomes ready for every clock pulse, the
    signals generated by the CPU will get extended.
  • 38:18 - 38:26
    At this point, when the valid data is ready,
    that is, somewhere between T3 and T4, when
  • 38:26 - 38:34
    the memory is ready with the data, the memory
    can pull this up again.
  • 38:34 - 38:43
    So when T4 comes, it sees that the CPU is
    ready and reading can be performed at that
  • 38:43 - 38:44
    point.
  • 38:44 - 38:45
    So this how it is done.
  • 38:45 - 38:48
    We had seen this earlier.
  • 38:48 - 38:59
    That is, T3 is an extra state that is included
    as a wait state; that is, the CPU was made
  • 38:59 - 39:06
    to wait during T3, and that was because of
    the ready input to the CPU.
  • 39:06 - 39:11
    The ready input is generated by the memory.
  • 39:11 - 39:15
    How and why is it generated?
  • 39:15 - 39:21
    It is known very well that the CPU’s fast
    memory is slow; that means a priori it is
  • 39:21 - 39:22
    known.
  • 39:22 - 39:30
    So, on seeing ready input, which is generated
    by the CPU as output ready input to the memory,
  • 39:30 - 39:35
    the memory responds immediately, saying that
    it is not going to be ready.
  • 39:35 - 39:42
    And how much delay is again depending on how
    many wait states must be introduced.
  • 39:42 - 39:50
    Since it is known that more than one state
    is not necessary, this will just pan for about
  • 39:50 - 39:52
    one state.
  • 39:52 - 39:58
    This is the very clear case of synchronous
    transmission.
  • 39:58 - 40:06
    The CPU memory makes use of a set of signal
    lines and the transmission is going on or
  • 40:06 - 40:12
    communication is going on between CPU and
    memory in a synchronized manner; it synchronizes
  • 40:12 - 40:16
    with every clock edge.
  • 40:16 - 40:24
    In the case of I/O, we just cannot guarantee
    that.
  • 40:24 - 40:31
    Some buses or devices may be fast, some devices
    will be slow.
  • 40:31 - 40:37
    And it may so happen that half way through
    the life cycle of the system, you may bring
  • 40:37 - 40:39
    in some new device.
  • 40:39 - 40:48
    We may bring in a new device, which may be
    fast or slow.
  • 40:48 - 40:53
    In those situations, specifically with reference
    to the I/O bus, it is meaningful to have an
  • 40:53 - 41:03
    asynchronous bus; meaning there will be a
    signal which says starts the I/O operation
  • 41:03 - 41:09
    and when the I/O has finished with it, it
    can tell that it has finished this job.
  • 41:09 - 41:15
    If it is a fast device, it is going to tell
    very fast, and the CPU will note it.
  • 41:15 - 41:24
    If it is a slow device, the device is going
    to take its own time and then inform.
  • 41:24 - 41:34
    So the master of the bus can initiate a data
    transfer and I/O will take its own time and
  • 41:34 - 41:40
    then it will communicate saying when it has
    finished the job, that is, the transfer.
  • 41:40 - 41:50
    In other words we can introduce what we may
    call us some communication between master
  • 41:50 - 42:03
    and slave in an interlocked manner; what is
    this communication?
  • 42:03 - 42:10
    The master says perform the data transfer
    and then slave responds to it.
  • 42:10 - 42:20
    So in an interlocked manner you establish
    the protocol of the communication.
  • 42:20 - 42:30
    That is, the master says the data is ready,
    now you can take it; the slave says I am taking
  • 42:30 - 42:36
    and this it says taking it own time.
  • 42:36 - 42:40
    So we call this master–slave interlocked
    communication.
  • 42:40 - 42:48
    It synchronizes with nothing; it will not
    go by the clock.
  • 42:48 - 42:52
    It need not go by the clock; the clock can
    very much be there.
  • 42:52 - 43:03
    Certainly it is not going to say that in this
    time slot something must be done; that restricting
  • 43:03 - 43:07
    is not there.
  • 43:07 - 43:14
    We also say that a set of signals that are
    used in the interlocked communication would
  • 43:14 - 43:21
    be something like the master and slave shaking
    hands.
  • 43:21 - 43:26
    So we refer to these signals involved in this
    as handshaking signals.
  • 43:26 - 43:37
    You may be able to appreciate why we say this.
  • 43:37 - 43:43
    When we meet a person, let us say we say hello.
  • 43:43 - 43:46
    And then, he also says hello.
  • 43:46 - 43:48
    Then you shake his hands and say how do you
    do.
  • 43:48 - 43:50
    And he also says how do you do.
  • 43:50 - 43:53
    It is somewhat like that: the master says
    hello, are you there?
  • 43:53 - 43:57
    The slave says, yes I am here.
  • 43:57 - 44:03
    Then the master says here is the data; the
    slave says I have taken the data.
  • 44:03 - 44:09
    That means a set of signals involved in this
    process are referred to as handshaking signals;
  • 44:09 - 44:18
    they see to it that the communication goes
    in an orderly manner, and for a person who
  • 44:18 - 44:25
    is not used to speaking very fast, takes his
    own time and then responds with the hello
  • 44:25 - 44:28
    or how do you do, it may be fast; some may
    be slow.
  • 44:28 - 44:36
    The same situation exists here too; in other
    words what we need is a few extra signals,
  • 44:36 - 44:38
    somewhat like this.
  • 44:38 - 44:42
    The master may place the address – let us
    just take a read cycle itself – the master
  • 44:42 - 44:50
    may place the address and then it may generate
    another signal, which says that the address
  • 44:50 - 45:03
    is placed and that signal will be sensed by
    the slave and it will respond saying I was
  • 45:03 - 45:08
    sensed there, and it will take the address.
  • 45:08 - 45:21
    Then the master will generate a read signal;
    and then the slave knows that from the address,
  • 45:21 - 45:26
    the slave must read and place the data.
  • 45:26 - 45:31
    After it places the data, it says now the
    data is ready.
  • 45:31 - 45:39
    The master will respond saying it will take
    the valid data that is available on the bus;
  • 45:39 - 45:44
    some extra signals are introduced.
  • 45:44 - 45:58
    So in this way, the address is placed; I will
    avoid this bipolar signal; I will just using
  • 45:58 - 46:02
    only one, just to show you the sequence.
  • 46:02 - 46:05
    Let us say it is something like this.
  • 46:05 - 46:12
    The address is placed; I am just assuming
    only one this thing at some time edge.
  • 46:12 - 46:22
    Since we have assumed read cycle, let us say
    that after the address is placed, the read
  • 46:22 - 46:30
    signal is
    also introduced.
  • 46:30 - 46:35
    Now there are different ways in which we can
    use a handshake signal; I am just assuming
  • 46:35 - 46:37
    one specific sequence.
  • 46:37 - 46:41
    So the address is placed and read is indicated.
  • 46:41 - 46:51
    From the master point of view, it can indicate
    that it wants the slave to respond by reading
  • 46:51 - 46:55
    the contents of the location, the address
    of which is given.
  • 46:55 - 47:03
    So after it has performed its job, the master
    indicates through one hand shake signal; we
  • 47:03 - 47:08
    will call it MSYNC.
  • 47:08 - 47:20
    This in fact is an indication
    that it wants reading to be performed by the
  • 47:20 - 47:29
    slave and it also gives indication of the
    address.
  • 47:29 - 47:46
    On seeing the MSYNC signal, the slave understands
    all this, and in response to this, the slave
  • 47:46 - 47:54
    can respond with the data, that is, the memory.
  • 47:54 - 48:00
    We assume this is memory response data.
  • 48:00 - 48:07
    Whatever may be the delay that delay is because
    of the memory?
  • 48:07 - 48:20
    After that delay, it generates the data and
    this is now available on the bus – valid
  • 48:20 - 48:24
    data.
  • 48:24 - 48:29
    Let us create some space for the other thing.
  • 48:29 - 48:41
    After the data is placed, in this case the
    memory can generate a similar slave SYNC signal
  • 48:41 - 48:52
    and indicate that after the instant, it will
    indicate that
  • 48:52 - 48:55
    from the point of view of slave, it has done
    its job.
  • 48:55 - 49:05
    The master is indicated by placing address
    and read: it is an indication to the slave
  • 49:05 - 49:09
    that the slave must perform read.
  • 49:09 - 49:20
    On seeing this master SYNC, the slave has
    responded by generating the data and placing
  • 49:20 - 49:22
    it on the bus.
  • 49:22 - 49:27
    After it has done its job, the slave is indicating.
  • 49:27 - 49:35
    Now this SSYNC is the signal given or generated
    by the slave.
  • 49:35 - 49:40
    On seeing this SSYNC signal, the master knows
    that whatever it wants is available on the
  • 49:40 - 49:48
    bus because after this instant, that is, on
    seeing the SSYNC signal, the master knows
  • 49:48 - 49:54
    that the required information is available.
  • 49:54 - 50:02
    Now the master, on seeing this, will read;
    that means, this read signal will continue
  • 50:02 - 50:09
    certainly beyond this for some time; after
    that it will terminate.
  • 50:09 - 50:20
    That means by this time the master has read
    the data, then after it has read the data
  • 50:20 - 50:27
    the master may terminate its signal, that
    is, after this instant when the data has been
  • 50:27 - 50:39
    read, the master will terminate its signal
    and on seeing this, the slave may respond
  • 50:39 - 50:42
    with a few things.
  • 50:42 - 50:53
    Suddenly on seeing this MSYNC going negative,
    the SSYNC also will be pulled down by the
  • 50:53 - 50:57
    slave.
  • 50:57 - 51:06
    This is the indication that the slave knows
    that the master has performed its job of reading,
  • 51:06 - 51:09
    now it is closing the whole show.
  • 51:09 - 51:17
    So we say that there are two hand shake signals,
    one MSYNC asserted by the master is an indication
  • 51:17 - 51:27
    to the slave that it wants something to be
    done and on doing that particular work, the
  • 51:27 - 51:39
    slave asserts the signal and on seeing the
    assertion of SSYNC, MSYNC, the master, concludes
  • 51:39 - 51:50
    its job of reading and then negates the MSYNC
    and on seeing the negation of MSYNC, the slave
  • 51:50 - 51:53
    also negates it.
  • 51:53 - 52:01
    So we see that the signals are asserted, that
    means the signals are placed and the signals
  • 52:01 - 52:11
    are negated; that is the signals are removed
    and you can see the specific sequence.
  • 52:11 - 52:17
    Now there is absolutely no clock that need
    be used here.
  • 52:17 - 52:22
    On seeing the signal, the other signal is
    generated; on seeing the negation of this
  • 52:22 - 52:29
    signal, the other signal is generated; and
    in between, the required activity is done.
  • 52:29 - 52:36
    This is the way the ASYNC bus will work and
    you need a set of extra signals for this.
  • 52:36 - 52:45
    These extra signals are something like a clock
    because they really do the timing, but it
  • 52:45 - 52:50
    is not strict clock periods like this.
  • 52:50 - 52:57
    So generally these are timing signals; that
    is about the synchronization.
  • 52:57 - 53:55
    We will see more about these processes in
    the next lecture.
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Claude Almansi edited English subtitles for Sandbox
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  • Revision 1 = provided subtitles for Lecture 1.2 of Prof. Scott Plous' Social Psychology course

  • Revision 1 = provided subtitles for Lecture 1.2 of Prof. Scott Plous' Social Psychology course

  • Revision 1 = provided subtitles for Lecture 1.2 of Prof. Scott Plous' Social Psychology course

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