WEBVTT 00:01:10.810 --> 00:01:18.100 In this last part in our series of lectures on computer organization, let us take a look 00:01:18.100 --> 00:01:20.380 at the bus. 00:01:20.380 --> 00:01:22.329 What is a bus? 00:01:22.329 --> 00:01:31.399 So far we had seen the blocks of CPU, memory, I/O and the interconnecting bus. 00:01:31.399 --> 00:01:37.679 On more than one occasion, I had pointed out that we have to evolve some kind of standardization 00:01:37.679 --> 00:01:46.070 so that the system from the bus we will see something uniform because you may be having 00:01:46.070 --> 00:01:51.030 different types of memory systems and you may be having different types of devices but 00:01:51.030 --> 00:01:55.159 the CPU must see something uniform on the bus on the bus end. 00:01:55.159 --> 00:02:02.180 In spite of all these, though we talk about standards, we would find that there are different 00:02:02.180 --> 00:02:09.389 standards; obviously because the CPU and memory work at some rate different from I/O. 00:02:09.389 --> 00:02:15.730 If at all CPU is directly involved, that is going to be at another rate; then, memory 00:02:15.730 --> 00:02:24.109 I/O will be a different rate; and in I/O, you have a spectrum from the lowest K speed 00:02:24.109 --> 00:02:26.440 to the fastest one. 00:02:26.440 --> 00:02:36.690 So generally, we would find that there are different types of buses and when a processor 00:02:36.690 --> 00:02:43.799 comes with some brand name in the market, you would find that that particular manufacturer 00:02:43.799 --> 00:02:46.340 comes out with its own bus also. 00:02:46.340 --> 00:02:56.160 By the time that particular bus gets standardized, you would find that the bus is no longer very 00:02:56.160 --> 00:03:01.710 relevant, mainly because the processor is outdated. 00:03:01.710 --> 00:03:10.200 Nevertheless, we can always talk in the case of bus; in general, about the specifications 00:03:10.200 --> 00:03:15.560 of the bus. 00:03:15.560 --> 00:03:22.360 Here there are certain things which you may find are common and there are certain things 00:03:22.360 --> 00:03:26.080 which would keep varying. 00:03:26.080 --> 00:03:32.170 Now while specifying a bus, what exactly is the bus; what is it we have talked about earlier? 00:03:32.170 --> 00:03:36.569 We have always said a bus is a set of signal lines. 00:03:36.569 --> 00:04:00.920 We had introduced the bus as a set of signal lines. 00:04:00.920 --> 00:04:10.690 Bus in fact is a term introduced by Americans; earlier the British used to call it highway. 00:04:10.690 --> 00:04:17.750 Now that particular term is coming in a different context like super highway for information 00:04:17.750 --> 00:04:18.750 and so on. 00:04:18.750 --> 00:04:22.660 Earlier they were calling it highway. 00:04:22.660 --> 00:04:29.400 Essentially on a highway something moves; but Americans used the bus. 00:04:29.400 --> 00:04:35.030 Now in the case of computer system, we can say the bus is like a highway over which the 00:04:35.030 --> 00:04:36.530 data moves – there is some communication. 00:04:36.530 --> 00:04:51.120 But Americans called it bus – since bus is a set of signal lines, these signal lines 00:04:51.120 --> 00:04:57.120 are carried over lines, which form conductors. 00:04:57.120 --> 00:05:09.520 So the bus has conductors and a bus is usually long; while trying to meet an electrical specification, 00:05:09.520 --> 00:05:20.190 you will find that you would need some current amplifiers, we call them current drivers. 00:05:20.190 --> 00:05:27.180 That means along with the bus or as part of a bus, you have drivers. 00:05:27.180 --> 00:05:31.870 So you can see that a bus has drivers and conductors and we are quite familiar with 00:05:31.870 --> 00:05:34.000 the term bus. 00:05:34.000 --> 00:05:43.680 Now let us go into certain aspects of the specifications. 00:05:43.680 --> 00:05:51.400 There are actually three types of specifications but usually in computer organization, or we 00:05:51.400 --> 00:05:55.889 may say even computer scientists will be concerned more with only one thing. 00:05:55.889 --> 00:06:00.729 That particular thing is called the logical specification of the bus. 00:06:00.729 --> 00:06:07.300 In fact all the time when we were talking about some transfer over the bus, we were 00:06:07.300 --> 00:06:10.229 indicating this. 00:06:10.229 --> 00:06:11.759 What is it we said earlier? 00:06:11.759 --> 00:06:19.550 We said the CPU places address on the bus and if it were a read cycle, the CPU also 00:06:19.550 --> 00:06:27.150 places a read signal on the bus, and then the memory responds with data and it puts 00:06:27.150 --> 00:06:28.250 it on the bus. 00:06:28.250 --> 00:06:31.530 CPU, of course, reads it in. 00:06:31.530 --> 00:06:38.789 So you can see that there is generation of address, signal generation of read signal 00:06:38.789 --> 00:06:41.870 and strobing the data that’s available. 00:06:41.870 --> 00:06:44.300 This is what we were talking about all the time. 00:06:44.300 --> 00:06:45.410 Now what is the data? 00:06:45.410 --> 00:06:49.699 Data is a pattern of 1s and 0s; it is a string of 1s and 0s. 00:06:49.699 --> 00:06:52.720 Similarly address also is a string. 00:06:52.720 --> 00:06:57.889 So all the time we were only talking about the logical aspect of it because we never 00:06:57.889 --> 00:07:07.190 said the data which is 1 means say 1 volt; 0 means say 0 volts or any such thing; we 00:07:07.190 --> 00:07:11.539 did not talk about any physical, real-world quantity. 00:07:11.539 --> 00:07:14.710 We were not referring to any physical quantity. 00:07:14.710 --> 00:07:18.220 We are talking about a read as a read signal, write as a write signal. 00:07:18.220 --> 00:07:22.910 We never said read means what must be the voltage and so on and so forth. 00:07:22.910 --> 00:07:27.569 So that is what we are talking about when we talk about the logical specification; another 00:07:27.569 --> 00:07:37.110 thing as you would have noticed is that we are talking about sequence of actions. 00:07:37.110 --> 00:07:44.750 What are the things we were mentioning? 00:07:44.750 --> 00:07:57.080 We said first address, then read and then the data comes, which is strobed, so we were 00:07:57.080 --> 00:07:58.449 talking about sequence also. 00:07:58.449 --> 00:08:07.409 In other words, the sequence of actions which is part of what we refer to as bus protocol, 00:08:07.409 --> 00:08:14.080 is only one specific way in which this read or write can be performed. 00:08:14.080 --> 00:08:23.860 So we talk about logical signals involved and then we also talk about the sequence in 00:08:23.860 --> 00:08:27.720 which the signals must be generated. 00:08:27.720 --> 00:08:34.260 Now generally when we discuss the bus in computer science, or from a computer scientist’s 00:08:34.260 --> 00:08:38.909 point of view, we will always be concerned with these logical aspects. 00:08:38.909 --> 00:08:45.920 But later as I was just trying to point out, there are two things: one is the electrical 00:08:45.920 --> 00:08:48.140 specification. 00:08:48.140 --> 00:08:55.480 So when we talk about the electrical specification of the bus, I have to say for instance what 00:08:55.480 --> 00:08:57.699 does 1 mean? 00:08:57.699 --> 00:09:11.480 Do 1 and 0 there refer to say some voltage signals or current signals or some other signals? 00:09:11.480 --> 00:09:20.900 And if for instance 1 and 0 will be represented by plus 5 V and 0 V or 3 V, plus 3 V and plus 00:09:20.900 --> 00:09:29.130 0.2 V or let us say plus 15 V and minus 15 V. 00:09:29.130 --> 00:09:33.400 All these things really refer to the physical quantities. 00:09:33.400 --> 00:09:38.530 They would come into the electrical specification of the bus. 00:09:38.530 --> 00:09:44.690 It is not enough if we say that the address is placed. 00:09:44.690 --> 00:10:00.519 We have to specify exactly what must be the levels of the voltage or current signals. 00:10:00.519 --> 00:10:13.700 Essentially we can just put it as physical specification, but then the mechanical specification 00:10:13.700 --> 00:10:16.030 of the bus also has to be specified. 00:10:16.030 --> 00:10:23.870 So together, these two form the physical part of the bus and this forms the logical part 00:10:23.870 --> 00:10:26.540 of the bus. 00:10:26.540 --> 00:10:33.040 One talks about the electrical signal levels and so on, the other one talks about the mechanical 00:10:33.040 --> 00:10:34.170 thing. 00:10:34.170 --> 00:10:44.329 So this would say how long the bus conductor can be and what sort of edge connector is 00:10:44.329 --> 00:10:50.959 used – is it something like 32 pin or 62 pin and if it is this pin, is it a parallel 00:10:50.959 --> 00:10:55.160 or are the pins parallel or staggered, etc. 00:10:55.160 --> 00:11:03.089 For instance, if we talk about the standard bus, we have specification along all the three 00:11:03.089 --> 00:11:04.089 dimensions. 00:11:04.089 --> 00:11:12.360 If we say multi-bus, there is a specific multi-bus connector and each of the multi-bus signals 00:11:12.360 --> 00:11:20.220 is going to be defined in terms of some electrical voltage current and so on. 00:11:20.220 --> 00:11:23.700 And then we also talk about this particular one. 00:11:23.700 --> 00:11:26.120 So essentially we will only concentrate on this. 00:11:26.120 --> 00:11:31.670 But let us not forget that there are these specifications also; somebody must concern 00:11:31.670 --> 00:11:33.850 with this; otherwise there is no standard. 00:11:33.850 --> 00:11:37.250 Now why must we be concerned even down to the level of mechanical? 00:11:37.250 --> 00:11:42.540 That is mainly because this is the one which is going to give freedom to the user. 00:11:42.540 --> 00:11:49.089 So if we say use multi-bus one connector or multi-bus two connectors or some other X bus, 00:11:49.089 --> 00:11:55.350 new bus, and then all he does is he goes to the shop and ask for that connector and then 00:11:55.350 --> 00:11:59.740 brings it and then machine properly without any difficulty. 00:11:59.740 --> 00:12:05.000 He is not going to be bothered about either logical aspect or electrical aspect; for him, 00:12:05.000 --> 00:12:11.209 when he keys in, there must be a display and that particular display must mean something 00:12:11.209 --> 00:12:14.270 to him at a higher level. 00:12:14.270 --> 00:12:20.050 Having said that, we will be concentrating on the logical aspects of this bus. 00:12:20.050 --> 00:12:24.170 We can note that essentially there are again three sections. 00:12:24.170 --> 00:12:30.640 The first one we may say is concerned with the data transfer. 00:12:30.640 --> 00:12:34.250 This is the one we keep talking all that time about. 00:12:34.250 --> 00:12:41.320 That is, we say that the CPU places address, indicates what type of transfer, read or write, 00:12:41.320 --> 00:12:48.010 input or output, whatever it wants, and then memory or I/O responds. 00:12:48.010 --> 00:12:53.760 So all these things: placing the address, placing the appropriate control signal, and 00:12:53.760 --> 00:12:57.800 then passing on the data will come under the data transfer aspect. 00:12:57.800 --> 00:13:04.810 Now as the CPU is involved in this data transfer because what is going on in any instruction 00:13:04.810 --> 00:13:11.060 cycle again and again is the same thing, fetching an instruction, interpreting, executing, as 00:13:11.060 --> 00:13:17.010 part of executing fetching a data, that is, instruction or data fetching – it all comes 00:13:17.010 --> 00:13:18.010 under the data transfer. 00:13:18.010 --> 00:13:20.720 This is what is going on in every instruction cycle. 00:13:20.720 --> 00:13:27.899 Now this is the essential thing as far as the processor is concerned. 00:13:27.899 --> 00:13:33.730 As this goes on some other device may indicate that it is ready; in the case of interrupt, 00:13:33.730 --> 00:13:35.589 is it not. 00:13:35.589 --> 00:13:42.420 Now in a system which has n number of devices, that is, multiple devices, we also said that 00:13:42.420 --> 00:13:48.339 we have to look in to the priority among these when there is a multiple request for this 00:13:48.339 --> 00:13:49.829 CPU attention. 00:13:49.829 --> 00:13:57.850 So we have to basically see that there is priority checking and so on. 00:13:57.850 --> 00:14:05.589 We may put this particular one as priority arbitration; meaning as CPU is busy with the 00:14:05.589 --> 00:14:22.130 transfer, then possibly there is some other specialized hardware unit, which looks into 00:14:22.130 --> 00:14:24.620 the action. 00:14:24.620 --> 00:14:31.399 Priority arbitration can go on in parallel with the data transfer. 00:14:31.399 --> 00:14:43.880 For instance as part of the some instruction cycle, when one of the n devices or two of 00:14:43.880 --> 00:14:50.790 the devices indicate that readiness, then there is a conflict. 00:14:50.790 --> 00:14:58.019 Now the priority arbitrator will look in to the requests and then will choose the higher 00:14:58.019 --> 00:15:05.329 priority device between those two so that when the instruction cycle is complete it 00:15:05.329 --> 00:15:09.769 can go ahead, that is, in the case of interrupt. 00:15:09.769 --> 00:15:17.200 So priority arbitration is another piece of action that goes on and we will have dedicated 00:15:17.200 --> 00:15:29.310 signal lines as part of the bus because then only two things can go on in parallel; otherwise 00:15:29.310 --> 00:15:30.690 it is not possible. 00:15:30.690 --> 00:15:36.940 If the same sets of signal lines are going to be used, one has to keep idling. 00:15:36.940 --> 00:15:43.199 For instance that was the situation in the case of DMA. 00:15:43.199 --> 00:15:50.550 The I/O is directly accessing the memory so CPU is going out of action. 00:15:50.550 --> 00:16:02.440 The third aspect of this bus we may just put in general as initialization. 00:16:02.440 --> 00:16:04.649 Different people may call it differently. 00:16:04.649 --> 00:16:11.399 What exactly we mean here is something to do with checking about the power, the system 00:16:11.399 --> 00:16:21.089 clock, and few other signal lines, which really not take direct part in data transfer or priority 00:16:21.089 --> 00:16:22.089 arbitration. 00:16:22.089 --> 00:16:23.990 There will be another set of signal lines. 00:16:23.990 --> 00:16:28.750 We may just call them for instance system reset signal. 00:16:28.750 --> 00:16:36.280 So that can come under the initialization and a few other things: system clock, system 00:16:36.280 --> 00:16:43.850 reset, some special signal lines, monitoring the power – all these things will come under 00:16:43.850 --> 00:16:46.959 this. 00:16:46.959 --> 00:16:52.259 So we as we talk about the data transfer; we should also take a look at what is going 00:16:52.259 --> 00:16:58.180 on in this and also know the functions of some of these because there is no standard 00:16:58.180 --> 00:17:00.480 about this particular thing. 00:17:00.480 --> 00:17:06.520 So generally when you study any bus, you may be able to identify a group of signals belonging 00:17:06.520 --> 00:17:12.760 to this or this or this category. 00:17:12.760 --> 00:17:19.290 Now there are different types of buses, we may say. 00:17:19.290 --> 00:17:24.780 Actually I am not talking about just the standard buses here. 00:17:24.780 --> 00:17:34.419 I am just trying to give what you may call a generic or general classification. 00:17:34.419 --> 00:17:35.950 What are the various things involved? 00:17:35.950 --> 00:17:42.610 For instance, we are not talking about multi-bus or a new bus or uni-bus or a mass bus and 00:17:42.610 --> 00:17:45.909 so on; we are discussing purely from functional point of view. 00:17:45.909 --> 00:17:56.169 Now we know that CPU and memory, both work at electronic speed. 00:17:56.169 --> 00:18:12.350 So it is meaningful to have a processor memory bus and have it somewhat different, distinct 00:18:12.350 --> 00:18:22.849 from what you may call the second one as an I/O bus mainly because in the case of processor 00:18:22.849 --> 00:18:30.750 memory, the transfer is going to be very fast whereas in the case of I/O bus, we do not 00:18:30.750 --> 00:18:31.750 know. 00:18:31.750 --> 00:18:39.150 We have devices with varying speeds, characteristics, and what not. 00:18:39.150 --> 00:18:47.390 Then there is another bus also that we talk about; that is generally called a back plane 00:18:47.390 --> 00:18:49.090 bus. 00:18:49.090 --> 00:18:56.920 In some systems we may not able to identify them separately. 00:18:56.920 --> 00:19:02.420 For instance the processor of the memory bus itself may act as a back plate bus; it is 00:19:02.420 --> 00:19:08.280 not necessary that all the three must exist in all the systems. 00:19:08.280 --> 00:19:15.669 Now let us say some one is looking up the system with an Intel processor. 00:19:15.669 --> 00:19:24.470 Then suited with that particular Intel processor, there may be certain memory chips. 00:19:24.470 --> 00:19:32.879 It is even possible that the manufacturer of the processor or the CPU has also come 00:19:32.879 --> 00:19:40.560 up with a set of memory chips, which would directly talk in the sense there will be some 00:19:40.560 --> 00:19:42.450 special features about that memory. 00:19:42.450 --> 00:19:50.050 For instance let us say suppose you have a processor with multiplexed bus, there is let 00:19:50.050 --> 00:19:52.770 us say address and data multiplex. 00:19:52.770 --> 00:20:00.000 If you have the memory chips or the memory controller, which goes with the chip in the 00:20:00.000 --> 00:20:07.179 memory bus system, it can take care of the multiplexing, so that internally it buffers 00:20:07.179 --> 00:20:09.419 and then de-multiplexes that. 00:20:09.419 --> 00:20:18.400 Then it is meaningful; and so what happens is this processor memory bus essentially we 00:20:18.400 --> 00:20:30.560 may say is a short bus and also it is a bus which does transaction as fast as possible. 00:20:30.560 --> 00:20:41.899 We can understand fast because, for this processor utilization to be the highest, maximal, it 00:20:41.899 --> 00:20:52.790 must be fast and invariably the processor, memory, and the bus are interconnecting the 00:20:52.790 --> 00:20:55.340 processor memory bus on a single board itself. 00:20:55.340 --> 00:21:04.230 That is why invariably we define that particular thing as a short bus and there may not be 00:21:04.230 --> 00:21:06.030 any standard about this also. 00:21:06.030 --> 00:21:11.340 For an Intel processor, there may be a set of things; for a Motorola processor there 00:21:11.340 --> 00:21:12.530 may be another set of things. 00:21:12.530 --> 00:21:21.720 It is all because of the signals that are generated by the respective processor. 00:21:21.720 --> 00:21:28.890 We can say that this processor memory bus is a proprietary bus because we have a specific 00:21:28.890 --> 00:21:35.470 processor and then we have specific memory requirement; it is not open for the general 00:21:35.470 --> 00:21:36.929 use. 00:21:36.929 --> 00:21:41.399 Now in the case of I/O bus, it is a different story. 00:21:41.399 --> 00:21:52.200 First of all, we have different types of devices to be connected; and second thing is that 00:21:52.200 --> 00:21:57.720 whereas in the case of processor memory even at the time of the design it is known how 00:21:57.720 --> 00:22:03.080 much of memory it has, at the time of the system installation, we do not know how many 00:22:03.080 --> 00:22:10.330 devices we want – may be during installation we would like to add a few more devices. 00:22:10.330 --> 00:22:15.320 Generally we would find this I/O bus is in contrast with the other one. 00:22:15.320 --> 00:22:26.220 I/O bus will be a long and slow bus; slow because essentially it is concerned with the 00:22:26.220 --> 00:22:27.570 I/O part. 00:22:27.570 --> 00:22:37.530 Generally it is lower compared with the other one, which is the processor memory bus, and 00:22:37.530 --> 00:22:44.450 it is also a long bus because you may have to have many connectors for the expansion 00:22:44.450 --> 00:22:49.870 of these devices and so on. 00:22:49.870 --> 00:22:56.409 So we have a range of speeds to be taken care of in the I/O; it is more or less standardized 00:22:56.409 --> 00:22:58.320 in the processor memory. 00:22:58.320 --> 00:23:03.389 The user is not directly concerned with this whereas the user is very much concerned with 00:23:03.389 --> 00:23:06.330 this. 00:23:06.330 --> 00:23:17.610 And the third one, the back plane bus, is on the PC board itself. 00:23:17.610 --> 00:23:26.390 You have the set of signal lines connected that is why it has derived the name back plane. 00:23:26.390 --> 00:23:35.570 As I said in some systems the back plane bus itself may be the processor memory bus. 00:23:35.570 --> 00:23:45.200 So through a few system configurations we will just see the essential difference between 00:23:45.200 --> 00:23:46.300 these back plane buses. 00:23:46.300 --> 00:23:52.201 But we take it as the back plane bus is one in which you have the entire set of signal 00:23:52.201 --> 00:24:03.340 lines on the PCB itself; so that is how it got the name back plane. 00:24:03.340 --> 00:24:12.740 Now regarding the requirements, it so happens that there are two requirements for a bus 00:24:12.740 --> 00:24:15.480 and they seem to be also conflicting. 00:24:15.480 --> 00:24:21.580 We generally talk about bus latency. 00:24:21.580 --> 00:24:23.700 What is the bus latency? 00:24:23.700 --> 00:24:32.030 Whenever there is a requirement of the bus for a data transfer, you would like to see 00:24:32.030 --> 00:24:40.510 that the bus is made available as fast as possible for the specific requirement. 00:24:40.510 --> 00:24:46.399 So we would have to see that the bus latency time must be minimized. 00:24:46.399 --> 00:24:58.020 The time associated with the bus latency must be minimized; that is, whenever there is a 00:24:58.020 --> 00:25:05.839 request for the bus, the bus must be made available with the least delay possible. 00:25:05.839 --> 00:25:11.670 Then the other factor is the bus bandwidth. 00:25:11.670 --> 00:25:23.230 This particular one conveys to us that if the bandwidth is high, more data can be transferred; 00:25:23.230 --> 00:25:30.260 that is, there is more efficient utilization. 00:25:30.260 --> 00:25:40.649 Now more data can be transferred if we can bunch all the data, buffer it and 00:25:40.649 --> 00:25:47.420 then send it with the least amount of interaction asking for address, control, things like that. 00:25:47.420 --> 00:25:53.630 As we have seen for instance in the DMA, the data is ready and available and then, like 00:25:53.630 --> 00:25:55.190 a machine gun, it keeps going. 00:25:55.190 --> 00:25:58.480 Every time we do not have to keep checking. 00:25:58.480 --> 00:26:10.369 So the bus bandwidth can be increased by what we say as buffering the data and transmitting 00:26:10.369 --> 00:26:23.440 block of data so that the time that is generally lost between two blocks or pieces of data 00:26:23.440 --> 00:26:28.490 can be further minimized. 00:26:28.490 --> 00:26:37.510 So there is buffering or storing more data before the actual transmission starts. 00:26:37.510 --> 00:26:42.179 So what we exactly gain here is that before the transmission, there may be some overheads 00:26:42.179 --> 00:26:48.830 and delay, but then there should not be any delay once the transmission starts, and once 00:26:48.830 --> 00:26:50.980 it starts, it goes very fast. 00:26:50.980 --> 00:27:00.050 While buffering a block and transmitting blocks of data, you maximize the bandwidth. 00:27:00.050 --> 00:27:01.050 Now what happens? 00:27:01.050 --> 00:27:06.980 When there is a block data transfer, the bus is not going to be available for some other 00:27:06.980 --> 00:27:09.669 device which requires it. 00:27:09.669 --> 00:27:19.640 That is because when the bus is being used by some other device, the one which requires 00:27:19.640 --> 00:27:23.600 the bus is going to wait; that is the reason. 00:27:23.600 --> 00:27:29.020 Now as we said the latency must be minimized; that is, the wait period must be minimized. 00:27:29.020 --> 00:27:36.130 We also say that the bus bandwidth must be maximized. 00:27:36.130 --> 00:27:43.230 Now while trying to maximize this, we ended up buffering the data and then transmitting 00:27:43.230 --> 00:27:51.860 the blocks of data; and while trying to maximize this, we see that the latency gets affected. 00:27:51.860 --> 00:28:00.960 That is, the device which requests the bus has to wait because some other large transfer 00:28:00.960 --> 00:28:03.129 is going on. 00:28:03.129 --> 00:28:09.710 So these two – bus latency and bus bandwidth – are actually conflicting requirements, 00:28:09.710 --> 00:28:18.770 so there must be some compromise between these; now this is very important. 00:28:18.770 --> 00:28:27.149 Talking about different types of buses from the timing point of view we talk about synchronous 00:28:27.149 --> 00:28:36.790 buses in which the transmission takes place. 00:28:36.790 --> 00:28:45.679 It is synchronized with some clock and of course the asynchronous bus. 00:28:45.679 --> 00:28:59.950 We have both types of buses; generally you will find that when synchronous bus is used 00:28:59.950 --> 00:29:04.869 everything must be known a priori. 00:29:04.869 --> 00:29:15.099 For instance, in the case of processor–memory interaction, the speed of the processor and 00:29:15.099 --> 00:29:20.080 how exactly memory is organized is known, whereas when it comes to I/O device we were 00:29:20.080 --> 00:29:21.640 not sure. 00:29:21.640 --> 00:29:29.109 We may add slow device and fast device later on also; a priori we will not have everything. 00:29:29.109 --> 00:29:35.400 So it may be better to say that it depends on the individual characteristic of the device. 00:29:35.400 --> 00:29:40.290 The bus transmission must be flexible; for this asynchronous is better. 00:29:40.290 --> 00:29:46.320 If everything is known a priori, then we can make those elements in synchronous, or rather 00:29:46.320 --> 00:29:47.849 work in synchronous. 00:29:47.849 --> 00:29:57.879 That is, for instance, we have talked about synchronous action earlier. 00:29:57.879 --> 00:30:11.970 Remember in the initial period we are talking about the states and in each state we were 00:30:11.970 --> 00:30:14.919 saying some minimum action was going on. 00:30:14.919 --> 00:30:21.919 The minimum action is going on and then the state itself is being defined by the clock 00:30:21.919 --> 00:30:23.859 of the system. 00:30:23.859 --> 00:30:28.230 That is in connection with CPU, we are talking about it. 00:30:28.230 --> 00:30:38.500 Remember then we were saying in state T1 the address is placed; let us say the address 00:30:38.500 --> 00:30:41.020 line may be either 1 or 0. 00:30:41.020 --> 00:30:50.320 So either it may be this way or it may this way; actually this particular one refers to 00:30:50.320 --> 00:30:54.510 rise time and fall time. 00:30:54.510 --> 00:31:07.089 So in T1 the addresses is placed on the bus and, let us say, in T2 the read control signal 00:31:07.089 --> 00:31:10.810 is generated. 00:31:10.810 --> 00:31:13.750 The read control signal is generated in T2. 00:31:13.750 --> 00:31:19.270 The address has been placed; the read control signal is generated; let us say that particular 00:31:19.270 --> 00:31:22.880 going signal is 0 to 1. 00:31:22.880 --> 00:31:31.890 That is, T1 address is placed; T2 wait control signal is generated; on seeing read, the memory 00:31:31.890 --> 00:31:38.889 responds with the data from the location indicated by the address. 00:31:38.889 --> 00:31:42.790 So from now from the memory side this is all this from the CPU side. 00:31:42.790 --> 00:31:51.550 Now to indicate that the memory is different from these we will call these as the data 00:31:51.550 --> 00:31:55.150 coming from the memory or memory dot data. 00:31:55.150 --> 00:32:08.070 The data that is coming some time after the memory sees the control signal read. 00:32:08.070 --> 00:32:12.659 So let us say there is some delay. 00:32:12.659 --> 00:32:16.820 I am just indicating the delay by this delta. 00:32:16.820 --> 00:32:23.060 There is some delay from the time the control signal is generated to the time the data is 00:32:23.060 --> 00:32:24.540 generated. 00:32:24.540 --> 00:32:32.960 This data actually refers to the data being 0. 00:32:32.960 --> 00:32:38.960 We do not know; may be some bit is 0, some bit is 1, so we would represent both. 00:32:38.960 --> 00:32:44.409 For instance if the memory responds to the 8-bit data, some bits will be 1; some bits 00:32:44.409 --> 00:32:46.770 will be 0. 00:32:46.770 --> 00:32:51.780 Some bits may continue to be 1; some bits may continue to be 0. 00:32:51.780 --> 00:33:02.760 So when we mark this way, it basically means it can be 1 or 0; this delta is the delay. 00:33:02.760 --> 00:33:10.640 This delay is due to the memory responding to the control signal read. 00:33:10.640 --> 00:33:20.010 There can also be delay introduced by the memory – that is when we talk about reading 00:33:20.010 --> 00:33:25.030 the data; delay with reference to the address also is possible. 00:33:25.030 --> 00:33:29.379 It is not shown here; here only the particular delay is shown. 00:33:29.379 --> 00:33:41.880 Now here you can see that assuming this delta, the delay, is less than one clock period, 00:33:41.880 --> 00:33:50.120 then we say that before T3 comes, this data can be read. 00:33:50.120 --> 00:33:53.930 This indicates that the read control signal in this says data is available. 00:33:53.930 --> 00:33:58.909 That is, we may refer to this as valid data. 00:33:58.909 --> 00:34:07.649 We say valid data because before this instant, the data was not valid; during this instant, 00:34:07.649 --> 00:34:11.050 there is some transition. 00:34:11.050 --> 00:34:13.130 Now the valid data is available. 00:34:13.130 --> 00:34:20.139 The CPU can actually read any time after this and even before T3. 00:34:20.139 --> 00:34:31.520 In this duration, the CPU can strobe it in, but if you want to be very careful you can 00:34:31.520 --> 00:34:38.349 see that at T3 this information is strobed, meaning, let us say something like this. 00:34:38.349 --> 00:34:46.300 For the read control this edge is used; this edge is used for reading. 00:34:46.300 --> 00:34:52.940 If that is so, we say that reading of the data is synchronized with the clock. 00:34:52.940 --> 00:35:01.940 Here this is a clear picture of synchronous transmission, synchronizing with the T1 clock, 00:35:01.940 --> 00:35:09.220 the address is generated; synchronizing with T2 clock, read control is generated; and in 00:35:09.220 --> 00:35:16.950 response to the read control, the memory places the data on the bus and synchronizing with 00:35:16.950 --> 00:35:23.010 T3, the data is read by the CPU. 00:35:23.010 --> 00:35:30.780 So this is the synchronized transmission, which means we know for sure that this delta 00:35:30.780 --> 00:35:35.580 is not going to be more than this period. 00:35:35.580 --> 00:35:38.960 That is, well before T3, the valid data is available. 00:35:38.960 --> 00:35:45.000 In case this is not available, we had talked about the situation earlier. 00:35:45.000 --> 00:35:52.520 In case before the next clock pulse the valid data is not available, that means memory is 00:35:52.520 --> 00:35:57.550 not responding to this control and address signals. 00:35:57.550 --> 00:36:00.130 It needs more time. 00:36:00.130 --> 00:36:10.770 We assume this particular period is 100 nanoseconds and the memory is delaying let us say by 150 00:36:10.770 --> 00:36:12.250 nanoseconds. 00:36:12.250 --> 00:36:16.440 That is, only 50 nanoseconds later, the valid data will be available, which means well before 00:36:16.440 --> 00:36:27.370 the next pulse, that is, T4, the data will be available. 00:36:27.370 --> 00:36:31.720 So reading cannot be performed here; so what will be done? 00:36:31.720 --> 00:36:40.070 What can be done is the read control signal must be further extended beyond and taken 00:36:40.070 --> 00:36:49.080 up to T4 because the data is not going to be available here. 00:36:49.080 --> 00:36:53.970 It is going to be available somewhere about 50 nanoseconds later. 00:36:53.970 --> 00:37:07.450 So the actual valid data will be available here itself; that means 1 clock pulse later, 00:37:07.450 --> 00:37:13.040 that data can be read. 00:37:13.040 --> 00:37:16.810 How is this achieved? 00:37:16.810 --> 00:37:23.210 The extension of this read pulse and delaying the reading is achieved as we had seen earlier. 00:37:23.210 --> 00:37:35.200 We said that the CPU can have a ready input, which can be used by the memory subsystem, 00:37:35.200 --> 00:37:48.410 and as soon as the memory system sees the read pulse, it can immediately say that the 00:37:48.410 --> 00:37:56.790 CPU, rather memory, is not ready. 00:37:56.790 --> 00:38:08.020 Now on seeing this ready input to the CPU, on seeing that memory is not ready, then until 00:38:08.020 --> 00:38:17.840 it becomes ready for every clock pulse, the signals generated by the CPU will get extended. 00:38:17.840 --> 00:38:26.260 At this point, when the valid data is ready, that is, somewhere between T3 and T4, when 00:38:26.260 --> 00:38:34.450 the memory is ready with the data, the memory can pull this up again. 00:38:34.450 --> 00:38:42.620 So when T4 comes, it sees that the CPU is ready and reading can be performed at that 00:38:42.620 --> 00:38:43.620 point. 00:38:43.620 --> 00:38:45.220 So this how it is done. 00:38:45.220 --> 00:38:48.070 We had seen this earlier. 00:38:48.070 --> 00:38:59.430 That is, T3 is an extra state that is included as a wait state; that is, the CPU was made 00:38:59.430 --> 00:39:06.090 to wait during T3, and that was because of the ready input to the CPU. 00:39:06.090 --> 00:39:11.430 The ready input is generated by the memory. 00:39:11.430 --> 00:39:14.941 How and why is it generated? 00:39:14.941 --> 00:39:21.250 It is known very well that the CPU’s fast memory is slow; that means a priori it is 00:39:21.250 --> 00:39:22.470 known. 00:39:22.470 --> 00:39:29.940 So, on seeing ready input, which is generated by the CPU as output ready input to the memory, 00:39:29.940 --> 00:39:34.820 the memory responds immediately, saying that it is not going to be ready. 00:39:34.820 --> 00:39:42.130 And how much delay is again depending on how many wait states must be introduced. 00:39:42.130 --> 00:39:50.040 Since it is known that more than one state is not necessary, this will just pan for about 00:39:50.040 --> 00:39:51.960 one state. 00:39:51.960 --> 00:39:57.950 This is the very clear case of synchronous transmission. 00:39:57.950 --> 00:40:06.470 The CPU memory makes use of a set of signal lines and the transmission is going on or 00:40:06.470 --> 00:40:12.070 communication is going on between CPU and memory in a synchronized manner; it synchronizes 00:40:12.070 --> 00:40:15.840 with every clock edge. 00:40:15.840 --> 00:40:23.630 In the case of I/O, we just cannot guarantee that. 00:40:23.630 --> 00:40:30.570 Some buses or devices may be fast, some devices will be slow. 00:40:30.570 --> 00:40:37.190 And it may so happen that half way through the life cycle of the system, you may bring 00:40:37.190 --> 00:40:39.080 in some new device. 00:40:39.080 --> 00:40:47.600 We may bring in a new device, which may be fast or slow. 00:40:47.600 --> 00:40:52.770 In those situations, specifically with reference to the I/O bus, it is meaningful to have an 00:40:52.770 --> 00:41:02.740 asynchronous bus; meaning there will be a signal which says starts the I/O operation 00:41:02.740 --> 00:41:09.240 and when the I/O has finished with it, it can tell that it has finished this job. 00:41:09.240 --> 00:41:15.200 If it is a fast device, it is going to tell very fast, and the CPU will note it. 00:41:15.200 --> 00:41:23.520 If it is a slow device, the device is going to take its own time and then inform. 00:41:23.520 --> 00:41:34.450 So the master of the bus can initiate a data transfer and I/O will take its own time and 00:41:34.450 --> 00:41:39.520 then it will communicate saying when it has finished the job, that is, the transfer. 00:41:39.520 --> 00:41:49.850 In other words we can introduce what we may call us some communication between master 00:41:49.850 --> 00:42:03.190 and slave in an interlocked manner; what is this communication? 00:42:03.190 --> 00:42:10.410 The master says perform the data transfer and then slave responds to it. 00:42:10.410 --> 00:42:20.210 So in an interlocked manner you establish the protocol of the communication. 00:42:20.210 --> 00:42:30.120 That is, the master says the data is ready, now you can take it; the slave says I am taking 00:42:30.120 --> 00:42:36.130 and this it says taking it own time. 00:42:36.130 --> 00:42:39.520 So we call this master–slave interlocked communication. 00:42:39.520 --> 00:42:47.770 It synchronizes with nothing; it will not go by the clock. 00:42:47.770 --> 00:42:52.260 It need not go by the clock; the clock can very much be there. 00:42:52.260 --> 00:43:02.940 Certainly it is not going to say that in this time slot something must be done; that restricting 00:43:02.940 --> 00:43:07.450 is not there. 00:43:07.450 --> 00:43:13.720 We also say that a set of signals that are used in the interlocked communication would 00:43:13.720 --> 00:43:20.950 be something like the master and slave shaking hands. 00:43:20.950 --> 00:43:26.430 So we refer to these signals involved in this as handshaking signals. 00:43:26.430 --> 00:43:37.140 You may be able to appreciate why we say this. 00:43:37.140 --> 00:43:42.640 When we meet a person, let us say we say hello. 00:43:42.640 --> 00:43:45.710 And then, he also says hello. 00:43:45.710 --> 00:43:48.080 Then you shake his hands and say how do you do. 00:43:48.080 --> 00:43:49.980 And he also says how do you do. 00:43:49.980 --> 00:43:53.450 It is somewhat like that: the master says hello, are you there? 00:43:53.450 --> 00:43:56.850 The slave says, yes I am here. 00:43:56.850 --> 00:44:03.350 Then the master says here is the data; the slave says I have taken the data. 00:44:03.350 --> 00:44:08.830 That means a set of signals involved in this process are referred to as handshaking signals; 00:44:08.830 --> 00:44:17.700 they see to it that the communication goes in an orderly manner, and for a person who 00:44:17.700 --> 00:44:25.080 is not used to speaking very fast, takes his own time and then responds with the hello 00:44:25.080 --> 00:44:28.350 or how do you do, it may be fast; some may be slow. 00:44:28.350 --> 00:44:36.240 The same situation exists here too; in other words what we need is a few extra signals, 00:44:36.240 --> 00:44:37.960 somewhat like this. 00:44:37.960 --> 00:44:42.260 The master may place the address – let us just take a read cycle itself – the master 00:44:42.260 --> 00:44:50.141 may place the address and then it may generate another signal, which says that the address 00:44:50.141 --> 00:45:03.320 is placed and that signal will be sensed by the slave and it will respond saying I was 00:45:03.320 --> 00:45:07.500 sensed there, and it will take the address. 00:45:07.500 --> 00:45:21.070 Then the master will generate a read signal; and then the slave knows that from the address, 00:45:21.070 --> 00:45:25.810 the slave must read and place the data. 00:45:25.810 --> 00:45:31.380 After it places the data, it says now the data is ready. 00:45:31.380 --> 00:45:39.360 The master will respond saying it will take the valid data that is available on the bus; 00:45:39.360 --> 00:45:43.810 some extra signals are introduced. 00:45:43.810 --> 00:45:58.140 So in this way, the address is placed; I will avoid this bipolar signal; I will just using 00:45:58.140 --> 00:46:02.410 only one, just to show you the sequence. 00:46:02.410 --> 00:46:04.640 Let us say it is something like this. 00:46:04.640 --> 00:46:11.650 The address is placed; I am just assuming only one this thing at some time edge. 00:46:11.650 --> 00:46:21.790 Since we have assumed read cycle, let us say that after the address is placed, the read 00:46:21.790 --> 00:46:30.040 signal is also introduced. 00:46:30.040 --> 00:46:34.820 Now there are different ways in which we can use a handshake signal; I am just assuming 00:46:34.820 --> 00:46:37.430 one specific sequence. 00:46:37.430 --> 00:46:40.920 So the address is placed and read is indicated. 00:46:40.920 --> 00:46:50.630 From the master point of view, it can indicate that it wants the slave to respond by reading 00:46:50.630 --> 00:46:54.800 the contents of the location, the address of which is given. 00:46:54.800 --> 00:47:03.300 So after it has performed its job, the master indicates through one hand shake signal; we 00:47:03.300 --> 00:47:07.610 will call it MSYNC. 00:47:07.610 --> 00:47:20.300 This in fact is an indication that it wants reading to be performed by the 00:47:20.300 --> 00:47:29.280 slave and it also gives indication of the address. 00:47:29.280 --> 00:47:46.380 On seeing the MSYNC signal, the slave understands all this, and in response to this, the slave 00:47:46.380 --> 00:47:53.980 can respond with the data, that is, the memory. 00:47:53.980 --> 00:47:59.850 We assume this is memory response data. 00:47:59.850 --> 00:48:07.460 Whatever may be the delay that delay is because of the memory? 00:48:07.460 --> 00:48:20.220 After that delay, it generates the data and this is now available on the bus – valid 00:48:20.220 --> 00:48:23.840 data. 00:48:23.840 --> 00:48:29.150 Let us create some space for the other thing. 00:48:29.150 --> 00:48:40.880 After the data is placed, in this case the memory can generate a similar slave SYNC signal 00:48:40.880 --> 00:48:51.840 and indicate that after the instant, it will indicate that 00:48:51.840 --> 00:48:54.600 from the point of view of slave, it has done its job. 00:48:54.600 --> 00:49:05.140 The master is indicated by placing address and read: it is an indication to the slave 00:49:05.140 --> 00:49:09.200 that the slave must perform read. 00:49:09.200 --> 00:49:20.030 On seeing this master SYNC, the slave has responded by generating the data and placing 00:49:20.030 --> 00:49:22.310 it on the bus. 00:49:22.310 --> 00:49:26.950 After it has done its job, the slave is indicating. 00:49:26.950 --> 00:49:34.730 Now this SSYNC is the signal given or generated by the slave. 00:49:34.730 --> 00:49:39.960 On seeing this SSYNC signal, the master knows that whatever it wants is available on the 00:49:39.960 --> 00:49:48.480 bus because after this instant, that is, on seeing the SSYNC signal, the master knows 00:49:48.480 --> 00:49:54.340 that the required information is available. 00:49:54.340 --> 00:50:01.960 Now the master, on seeing this, will read; that means, this read signal will continue 00:50:01.960 --> 00:50:08.670 certainly beyond this for some time; after that it will terminate. 00:50:08.670 --> 00:50:20.000 That means by this time the master has read the data, then after it has read the data 00:50:20.000 --> 00:50:27.220 the master may terminate its signal, that is, after this instant when the data has been 00:50:27.220 --> 00:50:39.300 read, the master will terminate its signal and on seeing this, the slave may respond 00:50:39.300 --> 00:50:42.250 with a few things. 00:50:42.250 --> 00:50:53.150 Suddenly on seeing this MSYNC going negative, the SSYNC also will be pulled down by the 00:50:53.150 --> 00:50:56.510 slave. 00:50:56.510 --> 00:51:05.560 This is the indication that the slave knows that the master has performed its job of reading, 00:51:05.560 --> 00:51:08.630 now it is closing the whole show. 00:51:08.630 --> 00:51:16.970 So we say that there are two hand shake signals, one MSYNC asserted by the master is an indication 00:51:16.970 --> 00:51:27.400 to the slave that it wants something to be done and on doing that particular work, the 00:51:27.400 --> 00:51:38.780 slave asserts the signal and on seeing the assertion of SSYNC, MSYNC, the master, concludes 00:51:38.780 --> 00:51:50.500 its job of reading and then negates the MSYNC and on seeing the negation of MSYNC, the slave 00:51:50.500 --> 00:51:52.690 also negates it. 00:51:52.690 --> 00:52:01.230 So we see that the signals are asserted, that means the signals are placed and the signals 00:52:01.230 --> 00:52:10.670 are negated; that is the signals are removed and you can see the specific sequence. 00:52:10.670 --> 00:52:17.230 Now there is absolutely no clock that need be used here. 00:52:17.230 --> 00:52:21.550 On seeing the signal, the other signal is generated; on seeing the negation of this 00:52:21.550 --> 00:52:28.970 signal, the other signal is generated; and in between, the required activity is done. 00:52:28.970 --> 00:52:36.040 This is the way the ASYNC bus will work and you need a set of extra signals for this. 00:52:36.040 --> 00:52:45.250 These extra signals are something like a clock because they really do the timing, but it 00:52:45.250 --> 00:52:50.160 is not strict clock periods like this. 00:52:50.160 --> 00:52:56.650 So generally these are timing signals; that is about the synchronization. 00:52:56.650 --> 00:53:54.990 We will see more about these processes in the next lecture.