[Script Info]
Title: 
[Events]
Format: Layer, Start, End, Style, Name, MarginL, MarginR, MarginV, Effect, Text
Dialogue: 0,0:01:10.81,0:01:18.10,Default,,0000,0000,0000,,In this last part in our series of lectures\Non computer organization, let us take a look
Dialogue: 0,0:01:18.10,0:01:20.38,Default,,0000,0000,0000,,at the bus.
Dialogue: 0,0:01:20.38,0:01:22.33,Default,,0000,0000,0000,,What is a bus?
Dialogue: 0,0:01:22.33,0:01:31.40,Default,,0000,0000,0000,,So far we had seen the blocks of CPU, memory,\NI/O and the interconnecting bus.
Dialogue: 0,0:01:31.40,0:01:37.68,Default,,0000,0000,0000,,On more than one occasion, I had pointed out\Nthat we have to evolve some kind of standardization
Dialogue: 0,0:01:37.68,0:01:46.07,Default,,0000,0000,0000,,so that the system from the bus we will see\Nsomething uniform because you may be having
Dialogue: 0,0:01:46.07,0:01:51.03,Default,,0000,0000,0000,,different types of memory systems and you\Nmay be having different types of devices but
Dialogue: 0,0:01:51.03,0:01:55.16,Default,,0000,0000,0000,,the CPU must see something uniform on the\Nbus on the bus end.
Dialogue: 0,0:01:55.16,0:02:02.18,Default,,0000,0000,0000,,In spite of all these, though we talk about\Nstandards, we would find that there are different
Dialogue: 0,0:02:02.18,0:02:09.39,Default,,0000,0000,0000,,standards; obviously because the CPU and memory\Nwork at some rate different from I/O.
Dialogue: 0,0:02:09.39,0:02:15.73,Default,,0000,0000,0000,,If at all CPU is directly involved, that is\Ngoing to be at another rate; then, memory
Dialogue: 0,0:02:15.73,0:02:24.11,Default,,0000,0000,0000,,I/O will be a different rate; and in I/O,\Nyou have a spectrum from the lowest K speed
Dialogue: 0,0:02:24.11,0:02:26.44,Default,,0000,0000,0000,,to the fastest one.
Dialogue: 0,0:02:26.44,0:02:36.69,Default,,0000,0000,0000,,So generally, we would find that there are\Ndifferent types of buses and when a processor
Dialogue: 0,0:02:36.69,0:02:43.80,Default,,0000,0000,0000,,comes with some brand name in the market,\Nyou would find that that particular manufacturer
Dialogue: 0,0:02:43.80,0:02:46.34,Default,,0000,0000,0000,,comes out with its own bus also.
Dialogue: 0,0:02:46.34,0:02:56.16,Default,,0000,0000,0000,,By the time that particular bus gets standardized,\Nyou would find that the bus is no longer very
Dialogue: 0,0:02:56.16,0:03:01.71,Default,,0000,0000,0000,,relevant, mainly because the processor is\Noutdated.
Dialogue: 0,0:03:01.71,0:03:10.20,Default,,0000,0000,0000,,Nevertheless, we can always talk in the case\Nof bus; in general, about the specifications
Dialogue: 0,0:03:10.20,0:03:15.56,Default,,0000,0000,0000,,of the bus.
Dialogue: 0,0:03:15.56,0:03:22.36,Default,,0000,0000,0000,,Here there are certain things which you may\Nfind are common and there are certain things
Dialogue: 0,0:03:22.36,0:03:26.08,Default,,0000,0000,0000,,which would keep varying.
Dialogue: 0,0:03:26.08,0:03:32.17,Default,,0000,0000,0000,,Now while specifying a bus, what exactly is\Nthe bus; what is it we have talked about earlier?
Dialogue: 0,0:03:32.17,0:03:36.57,Default,,0000,0000,0000,,We have always said a bus is a set of signal\Nlines.
Dialogue: 0,0:03:36.57,0:04:00.92,Default,,0000,0000,0000,,We had introduced the bus as a set of signal\Nlines.
Dialogue: 0,0:04:00.92,0:04:10.69,Default,,0000,0000,0000,,Bus in fact is a term introduced by Americans;\Nearlier the British used to call it highway.
Dialogue: 0,0:04:10.69,0:04:17.75,Default,,0000,0000,0000,,Now that particular term is coming in a different\Ncontext like super highway for information
Dialogue: 0,0:04:17.75,0:04:18.75,Default,,0000,0000,0000,,and so on.
Dialogue: 0,0:04:18.75,0:04:22.66,Default,,0000,0000,0000,,Earlier they were calling it highway.
Dialogue: 0,0:04:22.66,0:04:29.40,Default,,0000,0000,0000,,Essentially on a highway something moves;\Nbut Americans used the bus.
Dialogue: 0,0:04:29.40,0:04:35.03,Default,,0000,0000,0000,,Now in the case of computer system, we can\Nsay the bus is like a highway over which the
Dialogue: 0,0:04:35.03,0:04:36.53,Default,,0000,0000,0000,,data moves – there is some communication.
Dialogue: 0,0:04:36.53,0:04:51.12,Default,,0000,0000,0000,,But Americans called it bus – since bus\Nis a set of signal lines, these signal lines
Dialogue: 0,0:04:51.12,0:04:57.12,Default,,0000,0000,0000,,are carried over lines, which form conductors.
Dialogue: 0,0:04:57.12,0:05:09.52,Default,,0000,0000,0000,,So the bus has conductors and a bus is usually\Nlong; while trying to meet an electrical specification,
Dialogue: 0,0:05:09.52,0:05:20.19,Default,,0000,0000,0000,,you will find that you would need some current\Namplifiers, we call them current drivers.
Dialogue: 0,0:05:20.19,0:05:27.18,Default,,0000,0000,0000,,That means along with the bus or as part of\Na bus, you have drivers.
Dialogue: 0,0:05:27.18,0:05:31.87,Default,,0000,0000,0000,,So you can see that a bus has drivers and\Nconductors and we are quite familiar with
Dialogue: 0,0:05:31.87,0:05:34.00,Default,,0000,0000,0000,,the term bus.
Dialogue: 0,0:05:34.00,0:05:43.68,Default,,0000,0000,0000,,Now let us go into certain aspects of the\Nspecifications.
Dialogue: 0,0:05:43.68,0:05:51.40,Default,,0000,0000,0000,,There are actually three types of specifications\Nbut usually in computer organization, or we
Dialogue: 0,0:05:51.40,0:05:55.89,Default,,0000,0000,0000,,may say even computer scientists will be concerned\Nmore with only one thing.
Dialogue: 0,0:05:55.89,0:06:00.73,Default,,0000,0000,0000,,That particular thing is called the logical\Nspecification of the bus.
Dialogue: 0,0:06:00.73,0:06:07.30,Default,,0000,0000,0000,,In fact all the time when we were talking\Nabout some transfer over the bus, we were
Dialogue: 0,0:06:07.30,0:06:10.23,Default,,0000,0000,0000,,indicating this.
Dialogue: 0,0:06:10.23,0:06:11.76,Default,,0000,0000,0000,,What is it we said earlier?
Dialogue: 0,0:06:11.76,0:06:19.55,Default,,0000,0000,0000,,We said the CPU places address on the bus\Nand if it were a read cycle, the CPU also
Dialogue: 0,0:06:19.55,0:06:27.15,Default,,0000,0000,0000,,places a read signal on the bus, and then\Nthe memory responds with data and it puts
Dialogue: 0,0:06:27.15,0:06:28.25,Default,,0000,0000,0000,,it on the bus.
Dialogue: 0,0:06:28.25,0:06:31.53,Default,,0000,0000,0000,,CPU, of course, reads it in.
Dialogue: 0,0:06:31.53,0:06:38.79,Default,,0000,0000,0000,,So you can see that there is generation of\Naddress, signal generation of read signal
Dialogue: 0,0:06:38.79,0:06:41.87,Default,,0000,0000,0000,,and strobing the data that’s available.
Dialogue: 0,0:06:41.87,0:06:44.30,Default,,0000,0000,0000,,This is what we were talking about all the\Ntime.
Dialogue: 0,0:06:44.30,0:06:45.41,Default,,0000,0000,0000,,Now what is the data?
Dialogue: 0,0:06:45.41,0:06:49.70,Default,,0000,0000,0000,,Data is a pattern of 1s and 0s; it is a string\Nof 1s and 0s.
Dialogue: 0,0:06:49.70,0:06:52.72,Default,,0000,0000,0000,,Similarly address also is a string.
Dialogue: 0,0:06:52.72,0:06:57.89,Default,,0000,0000,0000,,So all the time we were only talking about\Nthe logical aspect of it because we never
Dialogue: 0,0:06:57.89,0:07:07.19,Default,,0000,0000,0000,,said the data which is 1 means say 1 volt;\N0 means say 0 volts or any such thing; we
Dialogue: 0,0:07:07.19,0:07:11.54,Default,,0000,0000,0000,,did not talk about any physical, real-world\Nquantity.
Dialogue: 0,0:07:11.54,0:07:14.71,Default,,0000,0000,0000,,We were not referring to any physical quantity.
Dialogue: 0,0:07:14.71,0:07:18.22,Default,,0000,0000,0000,,We are talking about a read as a read signal,\Nwrite as a write signal.
Dialogue: 0,0:07:18.22,0:07:22.91,Default,,0000,0000,0000,,We never said read means what must be the\Nvoltage and so on and so forth.
Dialogue: 0,0:07:22.91,0:07:27.57,Default,,0000,0000,0000,,So that is what we are talking about when\Nwe talk about the logical specification; another
Dialogue: 0,0:07:27.57,0:07:37.11,Default,,0000,0000,0000,,thing as you would have noticed is that we\Nare talking about sequence of actions.
Dialogue: 0,0:07:37.11,0:07:44.75,Default,,0000,0000,0000,,What are the things we were mentioning?
Dialogue: 0,0:07:44.75,0:07:57.08,Default,,0000,0000,0000,,We said first address, then read and then\Nthe data comes, which is strobed, so we were
Dialogue: 0,0:07:57.08,0:07:58.45,Default,,0000,0000,0000,,talking about sequence also.
Dialogue: 0,0:07:58.45,0:08:07.41,Default,,0000,0000,0000,,In other words, the sequence of actions which\Nis part of what we refer to as bus protocol,
Dialogue: 0,0:08:07.41,0:08:14.08,Default,,0000,0000,0000,,is only one specific way in which this read\Nor write can be performed.
Dialogue: 0,0:08:14.08,0:08:23.86,Default,,0000,0000,0000,,So we talk about logical signals involved\Nand then we also talk about the sequence in
Dialogue: 0,0:08:23.86,0:08:27.72,Default,,0000,0000,0000,,which the signals must be generated.
Dialogue: 0,0:08:27.72,0:08:34.26,Default,,0000,0000,0000,,Now generally when we discuss the bus in computer\Nscience, or from a computer scientist’s
Dialogue: 0,0:08:34.26,0:08:38.91,Default,,0000,0000,0000,,point of view, we will always be concerned\Nwith these logical aspects.
Dialogue: 0,0:08:38.91,0:08:45.92,Default,,0000,0000,0000,,But later as I was just trying to point out,\Nthere are two things: one is the electrical
Dialogue: 0,0:08:45.92,0:08:48.14,Default,,0000,0000,0000,,specification.
Dialogue: 0,0:08:48.14,0:08:55.48,Default,,0000,0000,0000,,So when we talk about the electrical specification\Nof the bus, I have to say for instance what
Dialogue: 0,0:08:55.48,0:08:57.70,Default,,0000,0000,0000,,does 1 mean?
Dialogue: 0,0:08:57.70,0:09:11.48,Default,,0000,0000,0000,,Do 1 and 0 there refer to say some voltage\Nsignals or current signals or some other signals?
Dialogue: 0,0:09:11.48,0:09:20.90,Default,,0000,0000,0000,,And if for instance 1 and 0 will be represented\Nby plus 5 V and 0 V or 3 V, plus 3 V and plus
Dialogue: 0,0:09:20.90,0:09:29.13,Default,,0000,0000,0000,,0.2 V or let us say plus 15 V and minus 15\NV.
Dialogue: 0,0:09:29.13,0:09:33.40,Default,,0000,0000,0000,,All these things really refer to the physical\Nquantities.
Dialogue: 0,0:09:33.40,0:09:38.53,Default,,0000,0000,0000,,They would come into the electrical specification\Nof the bus.
Dialogue: 0,0:09:38.53,0:09:44.69,Default,,0000,0000,0000,,It is not enough if we say that the address\Nis placed.
Dialogue: 0,0:09:44.69,0:10:00.52,Default,,0000,0000,0000,,We have to specify exactly what must be the\Nlevels of the voltage or current signals.
Dialogue: 0,0:10:00.52,0:10:13.70,Default,,0000,0000,0000,,Essentially we can just put it as physical\Nspecification, but then the mechanical specification
Dialogue: 0,0:10:13.70,0:10:16.03,Default,,0000,0000,0000,,of the bus also has to be specified.
Dialogue: 0,0:10:16.03,0:10:23.87,Default,,0000,0000,0000,,So together, these two form the physical part\Nof the bus and this forms the logical part
Dialogue: 0,0:10:23.87,0:10:26.54,Default,,0000,0000,0000,,of the bus.
Dialogue: 0,0:10:26.54,0:10:33.04,Default,,0000,0000,0000,,One talks about the electrical signal levels\Nand so on, the other one talks about the mechanical
Dialogue: 0,0:10:33.04,0:10:34.17,Default,,0000,0000,0000,,thing.
Dialogue: 0,0:10:34.17,0:10:44.33,Default,,0000,0000,0000,,So this would say how long the bus conductor\Ncan be and what sort of edge connector is
Dialogue: 0,0:10:44.33,0:10:50.96,Default,,0000,0000,0000,,used – is it something like 32 pin or 62\Npin and if it is this pin, is it a parallel
Dialogue: 0,0:10:50.96,0:10:55.16,Default,,0000,0000,0000,,or are the pins parallel or staggered, etc.
Dialogue: 0,0:10:55.16,0:11:03.09,Default,,0000,0000,0000,,For instance, if we talk about the standard\Nbus, we have specification along all the three
Dialogue: 0,0:11:03.09,0:11:04.09,Default,,0000,0000,0000,,dimensions.
Dialogue: 0,0:11:04.09,0:11:12.36,Default,,0000,0000,0000,,If we say multi-bus, there is a specific multi-bus\Nconnector and each of the multi-bus signals
Dialogue: 0,0:11:12.36,0:11:20.22,Default,,0000,0000,0000,,is going to be defined in terms of some electrical\Nvoltage current and so on.
Dialogue: 0,0:11:20.22,0:11:23.70,Default,,0000,0000,0000,,And then we also talk about this particular\None.
Dialogue: 0,0:11:23.70,0:11:26.12,Default,,0000,0000,0000,,So essentially we will only concentrate on\Nthis.
Dialogue: 0,0:11:26.12,0:11:31.67,Default,,0000,0000,0000,,But let us not forget that there are these\Nspecifications also; somebody must concern
Dialogue: 0,0:11:31.67,0:11:33.85,Default,,0000,0000,0000,,with this; otherwise there is no standard.
Dialogue: 0,0:11:33.85,0:11:37.25,Default,,0000,0000,0000,,Now why must we be concerned even down to\Nthe level of mechanical?
Dialogue: 0,0:11:37.25,0:11:42.54,Default,,0000,0000,0000,,That is mainly because this is the one which\Nis going to give freedom to the user.
Dialogue: 0,0:11:42.54,0:11:49.09,Default,,0000,0000,0000,,So if we say use multi-bus one connector or\Nmulti-bus two connectors or some other X bus,
Dialogue: 0,0:11:49.09,0:11:55.35,Default,,0000,0000,0000,,new bus, and then all he does is he goes to\Nthe shop and ask for that connector and then
Dialogue: 0,0:11:55.35,0:11:59.74,Default,,0000,0000,0000,,brings it and then machine properly without\Nany difficulty.
Dialogue: 0,0:11:59.74,0:12:05.00,Default,,0000,0000,0000,,He is not going to be bothered about either\Nlogical aspect or electrical aspect; for him,
Dialogue: 0,0:12:05.00,0:12:11.21,Default,,0000,0000,0000,,when he keys in, there must be a display and\Nthat particular display must mean something
Dialogue: 0,0:12:11.21,0:12:14.27,Default,,0000,0000,0000,,to him at a higher level.
Dialogue: 0,0:12:14.27,0:12:20.05,Default,,0000,0000,0000,,Having said that, we will be concentrating\Non the logical aspects of this bus.
Dialogue: 0,0:12:20.05,0:12:24.17,Default,,0000,0000,0000,,We can note that essentially there are again\Nthree sections.
Dialogue: 0,0:12:24.17,0:12:30.64,Default,,0000,0000,0000,,The first one we may say is concerned with\Nthe data transfer.
Dialogue: 0,0:12:30.64,0:12:34.25,Default,,0000,0000,0000,,This is the one we keep talking all that time\Nabout.
Dialogue: 0,0:12:34.25,0:12:41.32,Default,,0000,0000,0000,,That is, we say that the CPU places address,\Nindicates what type of transfer, read or write,
Dialogue: 0,0:12:41.32,0:12:48.01,Default,,0000,0000,0000,,input or output, whatever it wants, and then\Nmemory or I/O responds.
Dialogue: 0,0:12:48.01,0:12:53.76,Default,,0000,0000,0000,,So all these things: placing the address,\Nplacing the appropriate control signal, and
Dialogue: 0,0:12:53.76,0:12:57.80,Default,,0000,0000,0000,,then passing on the data will come under the\Ndata transfer aspect.
Dialogue: 0,0:12:57.80,0:13:04.81,Default,,0000,0000,0000,,Now as the CPU is involved in this data transfer\Nbecause what is going on in any instruction
Dialogue: 0,0:13:04.81,0:13:11.06,Default,,0000,0000,0000,,cycle again and again is the same thing, fetching\Nan instruction, interpreting, executing, as
Dialogue: 0,0:13:11.06,0:13:17.01,Default,,0000,0000,0000,,part of executing fetching a data, that is,\Ninstruction or data fetching – it all comes
Dialogue: 0,0:13:17.01,0:13:18.01,Default,,0000,0000,0000,,under the data transfer.
Dialogue: 0,0:13:18.01,0:13:20.72,Default,,0000,0000,0000,,This is what is going on in every instruction\Ncycle.
Dialogue: 0,0:13:20.72,0:13:27.90,Default,,0000,0000,0000,,Now this is the essential thing as far as\Nthe processor is concerned.
Dialogue: 0,0:13:27.90,0:13:33.73,Default,,0000,0000,0000,,As this goes on some other device may indicate\Nthat it is ready; in the case of interrupt,
Dialogue: 0,0:13:33.73,0:13:35.59,Default,,0000,0000,0000,,is it not.
Dialogue: 0,0:13:35.59,0:13:42.42,Default,,0000,0000,0000,,Now in a system which has n number of devices,\Nthat is, multiple devices, we also said that
Dialogue: 0,0:13:42.42,0:13:48.34,Default,,0000,0000,0000,,we have to look in to the priority among these\Nwhen there is a multiple request for this
Dialogue: 0,0:13:48.34,0:13:49.83,Default,,0000,0000,0000,,CPU attention.
Dialogue: 0,0:13:49.83,0:13:57.85,Default,,0000,0000,0000,,So we have to basically see that there is\Npriority checking and so on.
Dialogue: 0,0:13:57.85,0:14:05.59,Default,,0000,0000,0000,,We may put this particular one as priority\Narbitration; meaning as CPU is busy with the
Dialogue: 0,0:14:05.59,0:14:22.13,Default,,0000,0000,0000,,transfer, then possibly there is some other\Nspecialized hardware unit, which looks into
Dialogue: 0,0:14:22.13,0:14:24.62,Default,,0000,0000,0000,,the action.
Dialogue: 0,0:14:24.62,0:14:31.40,Default,,0000,0000,0000,,Priority arbitration can go on in parallel\Nwith the data transfer.
Dialogue: 0,0:14:31.40,0:14:43.88,Default,,0000,0000,0000,,For instance as part of the some instruction\Ncycle, when one of the n devices or two of
Dialogue: 0,0:14:43.88,0:14:50.79,Default,,0000,0000,0000,,the devices indicate that readiness, then\Nthere is a conflict.
Dialogue: 0,0:14:50.79,0:14:58.02,Default,,0000,0000,0000,,Now the priority arbitrator will look in to\Nthe requests and then will choose the higher
Dialogue: 0,0:14:58.02,0:15:05.33,Default,,0000,0000,0000,,priority device between those two so that\Nwhen the instruction cycle is complete it
Dialogue: 0,0:15:05.33,0:15:09.77,Default,,0000,0000,0000,,can go ahead, that is, in the case of interrupt.
Dialogue: 0,0:15:09.77,0:15:17.20,Default,,0000,0000,0000,,So priority arbitration is another piece of\Naction that goes on and we will have dedicated
Dialogue: 0,0:15:17.20,0:15:29.31,Default,,0000,0000,0000,,signal lines as part of the bus because then\Nonly two things can go on in parallel; otherwise
Dialogue: 0,0:15:29.31,0:15:30.69,Default,,0000,0000,0000,,it is not possible.
Dialogue: 0,0:15:30.69,0:15:36.94,Default,,0000,0000,0000,,If the same sets of signal lines are going\Nto be used, one has to keep idling.
Dialogue: 0,0:15:36.94,0:15:43.20,Default,,0000,0000,0000,,For instance that was the situation in the\Ncase of DMA.
Dialogue: 0,0:15:43.20,0:15:50.55,Default,,0000,0000,0000,,The I/O is directly accessing the memory so\NCPU is going out of action.
Dialogue: 0,0:15:50.55,0:16:02.44,Default,,0000,0000,0000,,The third aspect of this bus we may just put\Nin general as initialization.
Dialogue: 0,0:16:02.44,0:16:04.65,Default,,0000,0000,0000,,Different people may call it differently.
Dialogue: 0,0:16:04.65,0:16:11.40,Default,,0000,0000,0000,,What exactly we mean here is something to\Ndo with checking about the power, the system
Dialogue: 0,0:16:11.40,0:16:21.09,Default,,0000,0000,0000,,clock, and few other signal lines, which really\Nnot take direct part in data transfer or priority
Dialogue: 0,0:16:21.09,0:16:22.09,Default,,0000,0000,0000,,arbitration.
Dialogue: 0,0:16:22.09,0:16:23.99,Default,,0000,0000,0000,,There will be another set of signal lines.
Dialogue: 0,0:16:23.99,0:16:28.75,Default,,0000,0000,0000,,We may just call them for instance system\Nreset signal.
Dialogue: 0,0:16:28.75,0:16:36.28,Default,,0000,0000,0000,,So that can come under the initialization\Nand a few other things: system clock, system
Dialogue: 0,0:16:36.28,0:16:43.85,Default,,0000,0000,0000,,reset, some special signal lines, monitoring\Nthe power – all these things will come under
Dialogue: 0,0:16:43.85,0:16:46.96,Default,,0000,0000,0000,,this.
Dialogue: 0,0:16:46.96,0:16:52.26,Default,,0000,0000,0000,,So we as we talk about the data transfer;\Nwe should also take a look at what is going
Dialogue: 0,0:16:52.26,0:16:58.18,Default,,0000,0000,0000,,on in this and also know the functions of\Nsome of these because there is no standard
Dialogue: 0,0:16:58.18,0:17:00.48,Default,,0000,0000,0000,,about this particular thing.
Dialogue: 0,0:17:00.48,0:17:06.52,Default,,0000,0000,0000,,So generally when you study any bus, you may\Nbe able to identify a group of signals belonging
Dialogue: 0,0:17:06.52,0:17:12.76,Default,,0000,0000,0000,,to this or this or this category.
Dialogue: 0,0:17:12.76,0:17:19.29,Default,,0000,0000,0000,,Now there are different types of buses, we\Nmay say.
Dialogue: 0,0:17:19.29,0:17:24.78,Default,,0000,0000,0000,,Actually I am not talking about just the standard\Nbuses here.
Dialogue: 0,0:17:24.78,0:17:34.42,Default,,0000,0000,0000,,I am just trying to give what you may call\Na generic or general classification.
Dialogue: 0,0:17:34.42,0:17:35.95,Default,,0000,0000,0000,,What are the various things involved?
Dialogue: 0,0:17:35.95,0:17:42.61,Default,,0000,0000,0000,,For instance, we are not talking about multi-bus\Nor a new bus or uni-bus or a mass bus and
Dialogue: 0,0:17:42.61,0:17:45.91,Default,,0000,0000,0000,,so on; we are discussing purely from functional\Npoint of view.
Dialogue: 0,0:17:45.91,0:17:56.17,Default,,0000,0000,0000,,Now we know that CPU and memory, both work\Nat electronic speed.
Dialogue: 0,0:17:56.17,0:18:12.35,Default,,0000,0000,0000,,So it is meaningful to have a processor memory\Nbus and have it somewhat different, distinct
Dialogue: 0,0:18:12.35,0:18:22.85,Default,,0000,0000,0000,,from what you may call the second one as an\NI/O bus mainly because in the case of processor
Dialogue: 0,0:18:22.85,0:18:30.75,Default,,0000,0000,0000,,memory, the transfer is going to be very fast\Nwhereas in the case of I/O bus, we do not
Dialogue: 0,0:18:30.75,0:18:31.75,Default,,0000,0000,0000,,know.
Dialogue: 0,0:18:31.75,0:18:39.15,Default,,0000,0000,0000,,We have devices with varying speeds, characteristics,\Nand what not.
Dialogue: 0,0:18:39.15,0:18:47.39,Default,,0000,0000,0000,,Then there is another bus also that we talk\Nabout; that is generally called a back plane
Dialogue: 0,0:18:47.39,0:18:49.09,Default,,0000,0000,0000,,bus.
Dialogue: 0,0:18:49.09,0:18:56.92,Default,,0000,0000,0000,,In some systems we may not able to identify\Nthem separately.
Dialogue: 0,0:18:56.92,0:19:02.42,Default,,0000,0000,0000,,For instance the processor of the memory bus\Nitself may act as a back plate bus; it is
Dialogue: 0,0:19:02.42,0:19:08.28,Default,,0000,0000,0000,,not necessary that all the three must exist\Nin all the systems.
Dialogue: 0,0:19:08.28,0:19:15.67,Default,,0000,0000,0000,,Now let us say some one is looking up the\Nsystem with an Intel processor.
Dialogue: 0,0:19:15.67,0:19:24.47,Default,,0000,0000,0000,,Then suited with that particular Intel processor,\Nthere may be certain memory chips.
Dialogue: 0,0:19:24.47,0:19:32.88,Default,,0000,0000,0000,,It is even possible that the manufacturer\Nof the processor or the CPU has also come
Dialogue: 0,0:19:32.88,0:19:40.56,Default,,0000,0000,0000,,up with a set of memory chips, which would\Ndirectly talk in the sense there will be some
Dialogue: 0,0:19:40.56,0:19:42.45,Default,,0000,0000,0000,,special features about that memory.
Dialogue: 0,0:19:42.45,0:19:50.05,Default,,0000,0000,0000,,For instance let us say suppose you have a\Nprocessor with multiplexed bus, there is let
Dialogue: 0,0:19:50.05,0:19:52.77,Default,,0000,0000,0000,,us say address and data multiplex.
Dialogue: 0,0:19:52.77,0:20:00.00,Default,,0000,0000,0000,,If you have the memory chips or the memory\Ncontroller, which goes with the chip in the
Dialogue: 0,0:20:00.00,0:20:07.18,Default,,0000,0000,0000,,memory bus system, it can take care of the\Nmultiplexing, so that internally it buffers
Dialogue: 0,0:20:07.18,0:20:09.42,Default,,0000,0000,0000,,and then de-multiplexes that.
Dialogue: 0,0:20:09.42,0:20:18.40,Default,,0000,0000,0000,,Then it is meaningful; and so what happens\Nis this processor memory bus essentially we
Dialogue: 0,0:20:18.40,0:20:30.56,Default,,0000,0000,0000,,may say is a short bus and also it is a bus\Nwhich does transaction as fast as possible.
Dialogue: 0,0:20:30.56,0:20:41.90,Default,,0000,0000,0000,,We can understand fast because, for this processor\Nutilization to be the highest, maximal, it
Dialogue: 0,0:20:41.90,0:20:52.79,Default,,0000,0000,0000,,must be fast and invariably the processor,\Nmemory, and the bus are interconnecting the
Dialogue: 0,0:20:52.79,0:20:55.34,Default,,0000,0000,0000,,processor memory bus on a single board itself.
Dialogue: 0,0:20:55.34,0:21:04.23,Default,,0000,0000,0000,,That is why invariably we define that particular\Nthing as a short bus and there may not be
Dialogue: 0,0:21:04.23,0:21:06.03,Default,,0000,0000,0000,,any standard about this also.
Dialogue: 0,0:21:06.03,0:21:11.34,Default,,0000,0000,0000,,For an Intel processor, there may be a set\Nof things; for a Motorola processor there
Dialogue: 0,0:21:11.34,0:21:12.53,Default,,0000,0000,0000,,may be another set of things.
Dialogue: 0,0:21:12.53,0:21:21.72,Default,,0000,0000,0000,,It is all because of the signals that are\Ngenerated by the respective processor.
Dialogue: 0,0:21:21.72,0:21:28.89,Default,,0000,0000,0000,,We can say that this processor memory bus\Nis a proprietary bus because we have a specific
Dialogue: 0,0:21:28.89,0:21:35.47,Default,,0000,0000,0000,,processor and then we have specific memory\Nrequirement; it is not open for the general
Dialogue: 0,0:21:35.47,0:21:36.93,Default,,0000,0000,0000,,use.
Dialogue: 0,0:21:36.93,0:21:41.40,Default,,0000,0000,0000,,Now in the case of I/O bus, it is a different\Nstory.
Dialogue: 0,0:21:41.40,0:21:52.20,Default,,0000,0000,0000,,First of all, we have different types of devices\Nto be connected; and second thing is that
Dialogue: 0,0:21:52.20,0:21:57.72,Default,,0000,0000,0000,,whereas in the case of processor memory even\Nat the time of the design it is known how
Dialogue: 0,0:21:57.72,0:22:03.08,Default,,0000,0000,0000,,much of memory it has, at the time of the\Nsystem installation, we do not know how many
Dialogue: 0,0:22:03.08,0:22:10.33,Default,,0000,0000,0000,,devices we want – may be during installation\Nwe would like to add a few more devices.
Dialogue: 0,0:22:10.33,0:22:15.32,Default,,0000,0000,0000,,Generally we would find this I/O bus is in\Ncontrast with the other one.
Dialogue: 0,0:22:15.32,0:22:26.22,Default,,0000,0000,0000,,I/O bus will be a long and slow bus; slow\Nbecause essentially it is concerned with the
Dialogue: 0,0:22:26.22,0:22:27.57,Default,,0000,0000,0000,,I/O part.
Dialogue: 0,0:22:27.57,0:22:37.53,Default,,0000,0000,0000,,Generally it is lower compared with the other\None, which is the processor memory bus, and
Dialogue: 0,0:22:37.53,0:22:44.45,Default,,0000,0000,0000,,it is also a long bus because you may have\Nto have many connectors for the expansion
Dialogue: 0,0:22:44.45,0:22:49.87,Default,,0000,0000,0000,,of these devices and so on.
Dialogue: 0,0:22:49.87,0:22:56.41,Default,,0000,0000,0000,,So we have a range of speeds to be taken care\Nof in the I/O; it is more or less standardized
Dialogue: 0,0:22:56.41,0:22:58.32,Default,,0000,0000,0000,,in the processor memory.
Dialogue: 0,0:22:58.32,0:23:03.39,Default,,0000,0000,0000,,The user is not directly concerned with this\Nwhereas the user is very much concerned with
Dialogue: 0,0:23:03.39,0:23:06.33,Default,,0000,0000,0000,,this.
Dialogue: 0,0:23:06.33,0:23:17.61,Default,,0000,0000,0000,,And the third one, the back plane bus, is\Non the PC board itself.
Dialogue: 0,0:23:17.61,0:23:26.39,Default,,0000,0000,0000,,You have the set of signal lines connected\Nthat is why it has derived the name back plane.
Dialogue: 0,0:23:26.39,0:23:35.57,Default,,0000,0000,0000,,As I said in some systems the back plane bus\Nitself may be the processor memory bus.
Dialogue: 0,0:23:35.57,0:23:45.20,Default,,0000,0000,0000,,So through a few system configurations we\Nwill just see the essential difference between
Dialogue: 0,0:23:45.20,0:23:46.30,Default,,0000,0000,0000,,these back plane buses.
Dialogue: 0,0:23:46.30,0:23:52.20,Default,,0000,0000,0000,,But we take it as the back plane bus is one\Nin which you have the entire set of signal
Dialogue: 0,0:23:52.20,0:24:03.34,Default,,0000,0000,0000,,lines on the PCB itself; so that is how it\Ngot the name back plane.
Dialogue: 0,0:24:03.34,0:24:12.74,Default,,0000,0000,0000,,Now regarding the requirements, it so happens\Nthat there are two requirements for a bus
Dialogue: 0,0:24:12.74,0:24:15.48,Default,,0000,0000,0000,,and they seem to be also conflicting.
Dialogue: 0,0:24:15.48,0:24:21.58,Default,,0000,0000,0000,,We generally talk about bus latency.
Dialogue: 0,0:24:21.58,0:24:23.70,Default,,0000,0000,0000,,What is the bus latency?
Dialogue: 0,0:24:23.70,0:24:32.03,Default,,0000,0000,0000,,Whenever there is a requirement of the bus\Nfor a data transfer, you would like to see
Dialogue: 0,0:24:32.03,0:24:40.51,Default,,0000,0000,0000,,that the bus is made available as fast as\Npossible for the specific requirement.
Dialogue: 0,0:24:40.51,0:24:46.40,Default,,0000,0000,0000,,So we would have to see that the bus latency\Ntime must be minimized.
Dialogue: 0,0:24:46.40,0:24:58.02,Default,,0000,0000,0000,,The time associated with the bus latency must\Nbe minimized; that is, whenever there is a
Dialogue: 0,0:24:58.02,0:25:05.84,Default,,0000,0000,0000,,request for the bus, the bus must be made\Navailable with the least delay possible.
Dialogue: 0,0:25:05.84,0:25:11.67,Default,,0000,0000,0000,,Then the other factor is the bus bandwidth.
Dialogue: 0,0:25:11.67,0:25:23.23,Default,,0000,0000,0000,,This particular one conveys to us that if\Nthe bandwidth is high, more data can be transferred;
Dialogue: 0,0:25:23.23,0:25:30.26,Default,,0000,0000,0000,,that is, there is more efficient utilization.
Dialogue: 0,0:25:30.26,0:25:40.65,Default,,0000,0000,0000,,Now more data can be transferred \Nif we can bunch all the data, buffer it and
Dialogue: 0,0:25:40.65,0:25:47.42,Default,,0000,0000,0000,,then send it with the least amount of interaction\Nasking for address, control, things like that.
Dialogue: 0,0:25:47.42,0:25:53.63,Default,,0000,0000,0000,,As we have seen for instance in the DMA, the\Ndata is ready and available and then, like
Dialogue: 0,0:25:53.63,0:25:55.19,Default,,0000,0000,0000,,a machine gun, it keeps going.
Dialogue: 0,0:25:55.19,0:25:58.48,Default,,0000,0000,0000,,Every time we do not have to keep checking.
Dialogue: 0,0:25:58.48,0:26:10.37,Default,,0000,0000,0000,,So the bus bandwidth can be increased by what\Nwe say as buffering the data and transmitting
Dialogue: 0,0:26:10.37,0:26:23.44,Default,,0000,0000,0000,,block of data so that the time that is generally\Nlost between two blocks or pieces of data
Dialogue: 0,0:26:23.44,0:26:28.49,Default,,0000,0000,0000,,can be further minimized.
Dialogue: 0,0:26:28.49,0:26:37.51,Default,,0000,0000,0000,,So there is buffering or storing more data\Nbefore the actual transmission starts.
Dialogue: 0,0:26:37.51,0:26:42.18,Default,,0000,0000,0000,,So what we exactly gain here is that before\Nthe transmission, there may be some overheads
Dialogue: 0,0:26:42.18,0:26:48.83,Default,,0000,0000,0000,,and delay, but then there should not be any\Ndelay once the transmission starts, and once
Dialogue: 0,0:26:48.83,0:26:50.98,Default,,0000,0000,0000,,it starts, it goes very fast.
Dialogue: 0,0:26:50.98,0:27:00.05,Default,,0000,0000,0000,,While buffering a block and transmitting blocks\Nof data, you maximize the bandwidth.
Dialogue: 0,0:27:00.05,0:27:01.05,Default,,0000,0000,0000,,Now what happens?
Dialogue: 0,0:27:01.05,0:27:06.98,Default,,0000,0000,0000,,When there is a block data transfer, the bus\Nis not going to be available for some other
Dialogue: 0,0:27:06.98,0:27:09.67,Default,,0000,0000,0000,,device which requires it.
Dialogue: 0,0:27:09.67,0:27:19.64,Default,,0000,0000,0000,,That is because when the bus is being used\Nby some other device, the one which requires
Dialogue: 0,0:27:19.64,0:27:23.60,Default,,0000,0000,0000,,the bus is going to wait; that is the reason.
Dialogue: 0,0:27:23.60,0:27:29.02,Default,,0000,0000,0000,,Now as we said the latency must be minimized;\Nthat is, the wait period must be minimized.
Dialogue: 0,0:27:29.02,0:27:36.13,Default,,0000,0000,0000,,We also say that the bus bandwidth must be\Nmaximized.
Dialogue: 0,0:27:36.13,0:27:43.23,Default,,0000,0000,0000,,Now while trying to maximize this, we ended\Nup buffering the data and then transmitting
Dialogue: 0,0:27:43.23,0:27:51.86,Default,,0000,0000,0000,,the blocks of data; and while trying to maximize\Nthis, we see that the latency gets affected.
Dialogue: 0,0:27:51.86,0:28:00.96,Default,,0000,0000,0000,,That is, the device which requests the bus\Nhas to wait because some other large transfer
Dialogue: 0,0:28:00.96,0:28:03.13,Default,,0000,0000,0000,,is going on.
Dialogue: 0,0:28:03.13,0:28:09.71,Default,,0000,0000,0000,,So these two – bus latency and bus bandwidth\N– are actually conflicting requirements,
Dialogue: 0,0:28:09.71,0:28:18.77,Default,,0000,0000,0000,,so there must be some compromise between these;\Nnow this is very important.
Dialogue: 0,0:28:18.77,0:28:27.15,Default,,0000,0000,0000,,Talking about different types of buses from\Nthe timing point of view we talk about synchronous
Dialogue: 0,0:28:27.15,0:28:36.79,Default,,0000,0000,0000,,buses in which the transmission takes place.
Dialogue: 0,0:28:36.79,0:28:45.68,Default,,0000,0000,0000,,It is synchronized with some clock and of\Ncourse the asynchronous bus.
Dialogue: 0,0:28:45.68,0:28:59.95,Default,,0000,0000,0000,,We have both types of buses; generally you\Nwill find that when synchronous bus is used
Dialogue: 0,0:28:59.95,0:29:04.87,Default,,0000,0000,0000,,everything must be known a priori.
Dialogue: 0,0:29:04.87,0:29:15.10,Default,,0000,0000,0000,,For instance, in the case of processor–memory\Ninteraction, the speed of the processor and
Dialogue: 0,0:29:15.10,0:29:20.08,Default,,0000,0000,0000,,how exactly memory is organized is known,\Nwhereas when it comes to I/O device we were
Dialogue: 0,0:29:20.08,0:29:21.64,Default,,0000,0000,0000,,not sure.
Dialogue: 0,0:29:21.64,0:29:29.11,Default,,0000,0000,0000,,We may add slow device and fast device later\Non also; a priori we will not have everything.
Dialogue: 0,0:29:29.11,0:29:35.40,Default,,0000,0000,0000,,So it may be better to say that it depends\Non the individual characteristic of the device.
Dialogue: 0,0:29:35.40,0:29:40.29,Default,,0000,0000,0000,,The bus transmission must be flexible; for\Nthis asynchronous is better.
Dialogue: 0,0:29:40.29,0:29:46.32,Default,,0000,0000,0000,,If everything is known a priori, then we can\Nmake those elements in synchronous, or rather
Dialogue: 0,0:29:46.32,0:29:47.85,Default,,0000,0000,0000,,work in synchronous.
Dialogue: 0,0:29:47.85,0:29:57.88,Default,,0000,0000,0000,,That is, for instance, we have talked about\Nsynchronous action earlier.
Dialogue: 0,0:29:57.88,0:30:11.97,Default,,0000,0000,0000,,Remember in the initial period we are talking\Nabout the states and in each state we were
Dialogue: 0,0:30:11.97,0:30:14.92,Default,,0000,0000,0000,,saying some minimum action was going on.
Dialogue: 0,0:30:14.92,0:30:21.92,Default,,0000,0000,0000,,The minimum action is going on and then the\Nstate itself is being defined by the clock
Dialogue: 0,0:30:21.92,0:30:23.86,Default,,0000,0000,0000,,of the system.
Dialogue: 0,0:30:23.86,0:30:28.23,Default,,0000,0000,0000,,That is in connection with CPU, we are talking\Nabout it.
Dialogue: 0,0:30:28.23,0:30:38.50,Default,,0000,0000,0000,,Remember then we were saying in state T1 the\Naddress is placed; let us say the address
Dialogue: 0,0:30:38.50,0:30:41.02,Default,,0000,0000,0000,,line may be either 1 or 0.
Dialogue: 0,0:30:41.02,0:30:50.32,Default,,0000,0000,0000,,So either it may be this way or it may this\Nway; actually this particular one refers to
Dialogue: 0,0:30:50.32,0:30:54.51,Default,,0000,0000,0000,,rise time and fall time.
Dialogue: 0,0:30:54.51,0:31:07.09,Default,,0000,0000,0000,,So in T1 the addresses is placed on the bus\Nand, let us say, in T2 the read control signal
Dialogue: 0,0:31:07.09,0:31:10.81,Default,,0000,0000,0000,,is generated.
Dialogue: 0,0:31:10.81,0:31:13.75,Default,,0000,0000,0000,,The read control signal is generated in T2.
Dialogue: 0,0:31:13.75,0:31:19.27,Default,,0000,0000,0000,,The address has been placed; the read control\Nsignal is generated; let us say that particular
Dialogue: 0,0:31:19.27,0:31:22.88,Default,,0000,0000,0000,,going signal is 0 to 1.
Dialogue: 0,0:31:22.88,0:31:31.89,Default,,0000,0000,0000,,That is, T1 address is placed; T2 wait control\Nsignal is generated; on seeing read, the memory
Dialogue: 0,0:31:31.89,0:31:38.89,Default,,0000,0000,0000,,responds with the data from the location indicated\Nby the address.
Dialogue: 0,0:31:38.89,0:31:42.79,Default,,0000,0000,0000,,So from now from the memory side this is all\Nthis from the CPU side.
Dialogue: 0,0:31:42.79,0:31:51.55,Default,,0000,0000,0000,,Now to indicate that the memory is different\Nfrom these we will call these as the data
Dialogue: 0,0:31:51.55,0:31:55.15,Default,,0000,0000,0000,,coming from the memory or memory dot data.
Dialogue: 0,0:31:55.15,0:32:08.07,Default,,0000,0000,0000,,The data that is coming some time after the\Nmemory sees the control signal read.
Dialogue: 0,0:32:08.07,0:32:12.66,Default,,0000,0000,0000,,So let us say there is some delay.
Dialogue: 0,0:32:12.66,0:32:16.82,Default,,0000,0000,0000,,I am just indicating the delay by this delta.
Dialogue: 0,0:32:16.82,0:32:23.06,Default,,0000,0000,0000,,There is some delay from the time the control\Nsignal is generated to the time the data is
Dialogue: 0,0:32:23.06,0:32:24.54,Default,,0000,0000,0000,,generated.
Dialogue: 0,0:32:24.54,0:32:32.96,Default,,0000,0000,0000,,This data actually refers to the data being\N0.
Dialogue: 0,0:32:32.96,0:32:38.96,Default,,0000,0000,0000,,We do not know; may be some bit is 0, some\Nbit is 1, so we would represent both.
Dialogue: 0,0:32:38.96,0:32:44.41,Default,,0000,0000,0000,,For instance if the memory responds to the\N8-bit data, some bits will be 1; some bits
Dialogue: 0,0:32:44.41,0:32:46.77,Default,,0000,0000,0000,,will be 0.
Dialogue: 0,0:32:46.77,0:32:51.78,Default,,0000,0000,0000,,Some bits may continue to be 1; some bits\Nmay continue to be 0.
Dialogue: 0,0:32:51.78,0:33:02.76,Default,,0000,0000,0000,,So when we mark this way, it basically means\Nit can be 1 or 0; this delta is the delay.
Dialogue: 0,0:33:02.76,0:33:10.64,Default,,0000,0000,0000,,This delay is due to the memory responding\Nto the control signal read.
Dialogue: 0,0:33:10.64,0:33:20.01,Default,,0000,0000,0000,,There can also be delay introduced by the\Nmemory – that is when we talk about reading
Dialogue: 0,0:33:20.01,0:33:25.03,Default,,0000,0000,0000,,the data; delay with reference to the address\Nalso is possible.
Dialogue: 0,0:33:25.03,0:33:29.38,Default,,0000,0000,0000,,It is not shown here; here only the particular\Ndelay is shown.
Dialogue: 0,0:33:29.38,0:33:41.88,Default,,0000,0000,0000,,Now here you can see that assuming this delta,\Nthe delay, is less than one clock period,
Dialogue: 0,0:33:41.88,0:33:50.12,Default,,0000,0000,0000,,then we say that before T3 comes, this data\Ncan be read.
Dialogue: 0,0:33:50.12,0:33:53.93,Default,,0000,0000,0000,,This indicates that the read control signal\Nin this says data is available.
Dialogue: 0,0:33:53.93,0:33:58.91,Default,,0000,0000,0000,,That is, we may refer to this as valid data.
Dialogue: 0,0:33:58.91,0:34:07.65,Default,,0000,0000,0000,,We say valid data because before this instant,\Nthe data was not valid; during this instant,
Dialogue: 0,0:34:07.65,0:34:11.05,Default,,0000,0000,0000,,there is some transition.
Dialogue: 0,0:34:11.05,0:34:13.13,Default,,0000,0000,0000,,Now the valid data is available.
Dialogue: 0,0:34:13.13,0:34:20.14,Default,,0000,0000,0000,,The CPU can actually read any time after this\Nand even before T3.
Dialogue: 0,0:34:20.14,0:34:31.52,Default,,0000,0000,0000,,In this duration, the CPU can strobe it in,\Nbut if you want to be very careful you can
Dialogue: 0,0:34:31.52,0:34:38.35,Default,,0000,0000,0000,,see that at T3 this information is strobed,\Nmeaning, let us say something like this.
Dialogue: 0,0:34:38.35,0:34:46.30,Default,,0000,0000,0000,,For the read control this edge is used; this\Nedge is used for reading.
Dialogue: 0,0:34:46.30,0:34:52.94,Default,,0000,0000,0000,,If that is so, we say that reading of the\Ndata is synchronized with the clock.
Dialogue: 0,0:34:52.94,0:35:01.94,Default,,0000,0000,0000,,Here this is a clear picture of synchronous\Ntransmission, synchronizing with the T1 clock,
Dialogue: 0,0:35:01.94,0:35:09.22,Default,,0000,0000,0000,,the address is generated; synchronizing with\NT2 clock, read control is generated; and in
Dialogue: 0,0:35:09.22,0:35:16.95,Default,,0000,0000,0000,,response to the read control, the memory places\Nthe data on the bus and synchronizing with
Dialogue: 0,0:35:16.95,0:35:23.01,Default,,0000,0000,0000,,T3, the data is read by the CPU.
Dialogue: 0,0:35:23.01,0:35:30.78,Default,,0000,0000,0000,,So this is the synchronized transmission,\Nwhich means we know for sure that this delta
Dialogue: 0,0:35:30.78,0:35:35.58,Default,,0000,0000,0000,,is not going to be more than this period.
Dialogue: 0,0:35:35.58,0:35:38.96,Default,,0000,0000,0000,,That is, well before T3, the valid data is\Navailable.
Dialogue: 0,0:35:38.96,0:35:45.00,Default,,0000,0000,0000,,In case this is not available, we had talked\Nabout the situation earlier.
Dialogue: 0,0:35:45.00,0:35:52.52,Default,,0000,0000,0000,,In case before the next clock pulse the valid\Ndata is not available, that means memory is
Dialogue: 0,0:35:52.52,0:35:57.55,Default,,0000,0000,0000,,not responding to this control and address\Nsignals.
Dialogue: 0,0:35:57.55,0:36:00.13,Default,,0000,0000,0000,,It needs more time.
Dialogue: 0,0:36:00.13,0:36:10.77,Default,,0000,0000,0000,,We assume this particular period is 100 nanoseconds\Nand the memory is delaying let us say by 150
Dialogue: 0,0:36:10.77,0:36:12.25,Default,,0000,0000,0000,,nanoseconds.
Dialogue: 0,0:36:12.25,0:36:16.44,Default,,0000,0000,0000,,That is, only 50 nanoseconds later, the valid\Ndata will be available, which means well before
Dialogue: 0,0:36:16.44,0:36:27.37,Default,,0000,0000,0000,,the next pulse, that is, T4, the data will\Nbe available.
Dialogue: 0,0:36:27.37,0:36:31.72,Default,,0000,0000,0000,,So reading cannot be performed here; so what\Nwill be done?
Dialogue: 0,0:36:31.72,0:36:40.07,Default,,0000,0000,0000,,What can be done is the read control signal\Nmust be further extended beyond and taken
Dialogue: 0,0:36:40.07,0:36:49.08,Default,,0000,0000,0000,,up to T4 because the data is not going to\Nbe available here.
Dialogue: 0,0:36:49.08,0:36:53.97,Default,,0000,0000,0000,,It is going to be available somewhere about\N50 nanoseconds later.
Dialogue: 0,0:36:53.97,0:37:07.45,Default,,0000,0000,0000,,So the actual valid data will be available\Nhere itself; that means 1 clock pulse later,
Dialogue: 0,0:37:07.45,0:37:13.04,Default,,0000,0000,0000,,that data can be read.
Dialogue: 0,0:37:13.04,0:37:16.81,Default,,0000,0000,0000,,How is this achieved?
Dialogue: 0,0:37:16.81,0:37:23.21,Default,,0000,0000,0000,,The extension of this read pulse and delaying\Nthe reading is achieved as we had seen earlier.
Dialogue: 0,0:37:23.21,0:37:35.20,Default,,0000,0000,0000,,We said that the CPU can have a ready input,\Nwhich can be used by the memory subsystem,
Dialogue: 0,0:37:35.20,0:37:48.41,Default,,0000,0000,0000,,and as soon as the memory system sees the\Nread pulse, it can immediately say that the
Dialogue: 0,0:37:48.41,0:37:56.79,Default,,0000,0000,0000,,CPU, rather memory, is not ready.
Dialogue: 0,0:37:56.79,0:38:08.02,Default,,0000,0000,0000,,Now on seeing this ready input to the CPU,\Non seeing that memory is not ready, then until
Dialogue: 0,0:38:08.02,0:38:17.84,Default,,0000,0000,0000,,it becomes ready for every clock pulse, the\Nsignals generated by the CPU will get extended.
Dialogue: 0,0:38:17.84,0:38:26.26,Default,,0000,0000,0000,,At this point, when the valid data is ready,\Nthat is, somewhere between T3 and T4, when
Dialogue: 0,0:38:26.26,0:38:34.45,Default,,0000,0000,0000,,the memory is ready with the data, the memory\Ncan pull this up again.
Dialogue: 0,0:38:34.45,0:38:42.62,Default,,0000,0000,0000,,So when T4 comes, it sees that the CPU is\Nready and reading can be performed at that
Dialogue: 0,0:38:42.62,0:38:43.62,Default,,0000,0000,0000,,point.
Dialogue: 0,0:38:43.62,0:38:45.22,Default,,0000,0000,0000,,So this how it is done.
Dialogue: 0,0:38:45.22,0:38:48.07,Default,,0000,0000,0000,,We had seen this earlier.
Dialogue: 0,0:38:48.07,0:38:59.43,Default,,0000,0000,0000,,That is, T3 is an extra state that is included\Nas a wait state; that is, the CPU was made
Dialogue: 0,0:38:59.43,0:39:06.09,Default,,0000,0000,0000,,to wait during T3, and that was because of\Nthe ready input to the CPU.
Dialogue: 0,0:39:06.09,0:39:11.43,Default,,0000,0000,0000,,The ready input is generated by the memory.
Dialogue: 0,0:39:11.43,0:39:14.94,Default,,0000,0000,0000,,How and why is it generated?
Dialogue: 0,0:39:14.94,0:39:21.25,Default,,0000,0000,0000,,It is known very well that the CPU’s fast\Nmemory is slow; that means a priori it is
Dialogue: 0,0:39:21.25,0:39:22.47,Default,,0000,0000,0000,,known.
Dialogue: 0,0:39:22.47,0:39:29.94,Default,,0000,0000,0000,,So, on seeing ready input, which is generated\Nby the CPU as output ready input to the memory,
Dialogue: 0,0:39:29.94,0:39:34.82,Default,,0000,0000,0000,,the memory responds immediately, saying that\Nit is not going to be ready.
Dialogue: 0,0:39:34.82,0:39:42.13,Default,,0000,0000,0000,,And how much delay is again depending on how\Nmany wait states must be introduced.
Dialogue: 0,0:39:42.13,0:39:50.04,Default,,0000,0000,0000,,Since it is known that more than one state\Nis not necessary, this will just pan for about
Dialogue: 0,0:39:50.04,0:39:51.96,Default,,0000,0000,0000,,one state.
Dialogue: 0,0:39:51.96,0:39:57.95,Default,,0000,0000,0000,,This is the very clear case of synchronous\Ntransmission.
Dialogue: 0,0:39:57.95,0:40:06.47,Default,,0000,0000,0000,,The CPU memory makes use of a set of signal\Nlines and the transmission is going on or
Dialogue: 0,0:40:06.47,0:40:12.07,Default,,0000,0000,0000,,communication is going on between CPU and\Nmemory in a synchronized manner; it synchronizes
Dialogue: 0,0:40:12.07,0:40:15.84,Default,,0000,0000,0000,,with every clock edge.
Dialogue: 0,0:40:15.84,0:40:23.63,Default,,0000,0000,0000,,In the case of I/O, we just cannot guarantee\Nthat.
Dialogue: 0,0:40:23.63,0:40:30.57,Default,,0000,0000,0000,,Some buses or devices may be fast, some devices\Nwill be slow.
Dialogue: 0,0:40:30.57,0:40:37.19,Default,,0000,0000,0000,,And it may so happen that half way through\Nthe life cycle of the system, you may bring
Dialogue: 0,0:40:37.19,0:40:39.08,Default,,0000,0000,0000,,in some new device.
Dialogue: 0,0:40:39.08,0:40:47.60,Default,,0000,0000,0000,,We may bring in a new device, which may be\Nfast or slow.
Dialogue: 0,0:40:47.60,0:40:52.77,Default,,0000,0000,0000,,In those situations, specifically with reference\Nto the I/O bus, it is meaningful to have an
Dialogue: 0,0:40:52.77,0:41:02.74,Default,,0000,0000,0000,,asynchronous bus; meaning there will be a\Nsignal which says starts the I/O operation
Dialogue: 0,0:41:02.74,0:41:09.24,Default,,0000,0000,0000,,and when the I/O has finished with it, it\Ncan tell that it has finished this job.
Dialogue: 0,0:41:09.24,0:41:15.20,Default,,0000,0000,0000,,If it is a fast device, it is going to tell\Nvery fast, and the CPU will note it.
Dialogue: 0,0:41:15.20,0:41:23.52,Default,,0000,0000,0000,,If it is a slow device, the device is going\Nto take its own time and then inform.
Dialogue: 0,0:41:23.52,0:41:34.45,Default,,0000,0000,0000,,So the master of the bus can initiate a data\Ntransfer and I/O will take its own time and
Dialogue: 0,0:41:34.45,0:41:39.52,Default,,0000,0000,0000,,then it will communicate saying when it has\Nfinished the job, that is, the transfer.
Dialogue: 0,0:41:39.52,0:41:49.85,Default,,0000,0000,0000,,In other words we can introduce what we may\Ncall us some communication between master
Dialogue: 0,0:41:49.85,0:42:03.19,Default,,0000,0000,0000,,and slave in an interlocked manner; what is\Nthis communication?
Dialogue: 0,0:42:03.19,0:42:10.41,Default,,0000,0000,0000,,The master says perform the data transfer\Nand then slave responds to it.
Dialogue: 0,0:42:10.41,0:42:20.21,Default,,0000,0000,0000,,So in an interlocked manner you establish\Nthe protocol of the communication.
Dialogue: 0,0:42:20.21,0:42:30.12,Default,,0000,0000,0000,,That is, the master says the data is ready,\Nnow you can take it; the slave says I am taking
Dialogue: 0,0:42:30.12,0:42:36.13,Default,,0000,0000,0000,,and this it says taking it own time.
Dialogue: 0,0:42:36.13,0:42:39.52,Default,,0000,0000,0000,,So we call this master–slave interlocked\Ncommunication.
Dialogue: 0,0:42:39.52,0:42:47.77,Default,,0000,0000,0000,,It synchronizes with nothing; it will not\Ngo by the clock.
Dialogue: 0,0:42:47.77,0:42:52.26,Default,,0000,0000,0000,,It need not go by the clock; the clock can\Nvery much be there.
Dialogue: 0,0:42:52.26,0:43:02.94,Default,,0000,0000,0000,,Certainly it is not going to say that in this\Ntime slot something must be done; that restricting
Dialogue: 0,0:43:02.94,0:43:07.45,Default,,0000,0000,0000,,is not there.
Dialogue: 0,0:43:07.45,0:43:13.72,Default,,0000,0000,0000,,We also say that a set of signals that are\Nused in the interlocked communication would
Dialogue: 0,0:43:13.72,0:43:20.95,Default,,0000,0000,0000,,be something like the master and slave shaking\Nhands.
Dialogue: 0,0:43:20.95,0:43:26.43,Default,,0000,0000,0000,,So we refer to these signals involved in this\Nas handshaking signals.
Dialogue: 0,0:43:26.43,0:43:37.14,Default,,0000,0000,0000,,You may be able to appreciate why we say this.
Dialogue: 0,0:43:37.14,0:43:42.64,Default,,0000,0000,0000,,When we meet a person, let us say we say hello.
Dialogue: 0,0:43:42.64,0:43:45.71,Default,,0000,0000,0000,,And then, he also says hello.
Dialogue: 0,0:43:45.71,0:43:48.08,Default,,0000,0000,0000,,Then you shake his hands and say how do you\Ndo.
Dialogue: 0,0:43:48.08,0:43:49.98,Default,,0000,0000,0000,,And he also says how do you do.
Dialogue: 0,0:43:49.98,0:43:53.45,Default,,0000,0000,0000,,It is somewhat like that: the master says\Nhello, are you there?
Dialogue: 0,0:43:53.45,0:43:56.85,Default,,0000,0000,0000,,The slave says, yes I am here.
Dialogue: 0,0:43:56.85,0:44:03.35,Default,,0000,0000,0000,,Then the master says here is the data; the\Nslave says I have taken the data.
Dialogue: 0,0:44:03.35,0:44:08.83,Default,,0000,0000,0000,,That means a set of signals involved in this\Nprocess are referred to as handshaking signals;
Dialogue: 0,0:44:08.83,0:44:17.70,Default,,0000,0000,0000,,they see to it that the communication goes\Nin an orderly manner, and for a person who
Dialogue: 0,0:44:17.70,0:44:25.08,Default,,0000,0000,0000,,is not used to speaking very fast, takes his\Nown time and then responds with the hello
Dialogue: 0,0:44:25.08,0:44:28.35,Default,,0000,0000,0000,,or how do you do, it may be fast; some may\Nbe slow.
Dialogue: 0,0:44:28.35,0:44:36.24,Default,,0000,0000,0000,,The same situation exists here too; in other\Nwords what we need is a few extra signals,
Dialogue: 0,0:44:36.24,0:44:37.96,Default,,0000,0000,0000,,somewhat like this.
Dialogue: 0,0:44:37.96,0:44:42.26,Default,,0000,0000,0000,,The master may place the address – let us\Njust take a read cycle itself – the master
Dialogue: 0,0:44:42.26,0:44:50.14,Default,,0000,0000,0000,,may place the address and then it may generate\Nanother signal, which says that the address
Dialogue: 0,0:44:50.14,0:45:03.32,Default,,0000,0000,0000,,is placed and that signal will be sensed by\Nthe slave and it will respond saying I was
Dialogue: 0,0:45:03.32,0:45:07.50,Default,,0000,0000,0000,,sensed there, and it will take the address.
Dialogue: 0,0:45:07.50,0:45:21.07,Default,,0000,0000,0000,,Then the master will generate a read signal;\Nand then the slave knows that from the address,
Dialogue: 0,0:45:21.07,0:45:25.81,Default,,0000,0000,0000,,the slave must read and place the data.
Dialogue: 0,0:45:25.81,0:45:31.38,Default,,0000,0000,0000,,After it places the data, it says now the\Ndata is ready.
Dialogue: 0,0:45:31.38,0:45:39.36,Default,,0000,0000,0000,,The master will respond saying it will take\Nthe valid data that is available on the bus;
Dialogue: 0,0:45:39.36,0:45:43.81,Default,,0000,0000,0000,,some extra signals are introduced.
Dialogue: 0,0:45:43.81,0:45:58.14,Default,,0000,0000,0000,,So in this way, the address is placed; I will\Navoid this bipolar signal; I will just using
Dialogue: 0,0:45:58.14,0:46:02.41,Default,,0000,0000,0000,,only one, just to show you the sequence.
Dialogue: 0,0:46:02.41,0:46:04.64,Default,,0000,0000,0000,,Let us say it is something like this.
Dialogue: 0,0:46:04.64,0:46:11.65,Default,,0000,0000,0000,,The address is placed; I am just assuming\Nonly one this thing at some time edge.
Dialogue: 0,0:46:11.65,0:46:21.79,Default,,0000,0000,0000,,Since we have assumed read cycle, let us say\Nthat after the address is placed, the read
Dialogue: 0,0:46:21.79,0:46:30.04,Default,,0000,0000,0000,,signal is \Nalso introduced.
Dialogue: 0,0:46:30.04,0:46:34.82,Default,,0000,0000,0000,,Now there are different ways in which we can\Nuse a handshake signal; I am just assuming
Dialogue: 0,0:46:34.82,0:46:37.43,Default,,0000,0000,0000,,one specific sequence.
Dialogue: 0,0:46:37.43,0:46:40.92,Default,,0000,0000,0000,,So the address is placed and read is indicated.
Dialogue: 0,0:46:40.92,0:46:50.63,Default,,0000,0000,0000,,From the master point of view, it can indicate\Nthat it wants the slave to respond by reading
Dialogue: 0,0:46:50.63,0:46:54.80,Default,,0000,0000,0000,,the contents of the location, the address\Nof which is given.
Dialogue: 0,0:46:54.80,0:47:03.30,Default,,0000,0000,0000,,So after it has performed its job, the master\Nindicates through one hand shake signal; we
Dialogue: 0,0:47:03.30,0:47:07.61,Default,,0000,0000,0000,,will call it MSYNC.
Dialogue: 0,0:47:07.61,0:47:20.30,Default,,0000,0000,0000,,This in fact is an indication \Nthat it wants reading to be performed by the
Dialogue: 0,0:47:20.30,0:47:29.28,Default,,0000,0000,0000,,slave and it also gives indication of the\Naddress.
Dialogue: 0,0:47:29.28,0:47:46.38,Default,,0000,0000,0000,,On seeing the MSYNC signal, the slave understands\Nall this, and in response to this, the slave
Dialogue: 0,0:47:46.38,0:47:53.98,Default,,0000,0000,0000,,can respond with the data, that is, the memory.
Dialogue: 0,0:47:53.98,0:47:59.85,Default,,0000,0000,0000,,We assume this is memory response data.
Dialogue: 0,0:47:59.85,0:48:07.46,Default,,0000,0000,0000,,Whatever may be the delay that delay is because\Nof the memory?
Dialogue: 0,0:48:07.46,0:48:20.22,Default,,0000,0000,0000,,After that delay, it generates the data and\Nthis is now available on the bus – valid
Dialogue: 0,0:48:20.22,0:48:23.84,Default,,0000,0000,0000,,data.
Dialogue: 0,0:48:23.84,0:48:29.15,Default,,0000,0000,0000,,Let us create some space for the other thing.
Dialogue: 0,0:48:29.15,0:48:40.88,Default,,0000,0000,0000,,After the data is placed, in this case the\Nmemory can generate a similar slave SYNC signal
Dialogue: 0,0:48:40.88,0:48:51.84,Default,,0000,0000,0000,,and indicate that after the instant, it will\Nindicate that
Dialogue: 0,0:48:51.84,0:48:54.60,Default,,0000,0000,0000,,from the point of view of slave, it has done\Nits job.
Dialogue: 0,0:48:54.60,0:49:05.14,Default,,0000,0000,0000,,The master is indicated by placing address\Nand read: it is an indication to the slave
Dialogue: 0,0:49:05.14,0:49:09.20,Default,,0000,0000,0000,,that the slave must perform read.
Dialogue: 0,0:49:09.20,0:49:20.03,Default,,0000,0000,0000,,On seeing this master SYNC, the slave has\Nresponded by generating the data and placing
Dialogue: 0,0:49:20.03,0:49:22.31,Default,,0000,0000,0000,,it on the bus.
Dialogue: 0,0:49:22.31,0:49:26.95,Default,,0000,0000,0000,,After it has done its job, the slave is indicating.
Dialogue: 0,0:49:26.95,0:49:34.73,Default,,0000,0000,0000,,Now this SSYNC is the signal given or generated\Nby the slave.
Dialogue: 0,0:49:34.73,0:49:39.96,Default,,0000,0000,0000,,On seeing this SSYNC signal, the master knows\Nthat whatever it wants is available on the
Dialogue: 0,0:49:39.96,0:49:48.48,Default,,0000,0000,0000,,bus because after this instant, that is, on\Nseeing the SSYNC signal, the master knows
Dialogue: 0,0:49:48.48,0:49:54.34,Default,,0000,0000,0000,,that the required information is available.
Dialogue: 0,0:49:54.34,0:50:01.96,Default,,0000,0000,0000,,Now the master, on seeing this, will read;\Nthat means, this read signal will continue
Dialogue: 0,0:50:01.96,0:50:08.67,Default,,0000,0000,0000,,certainly beyond this for some time; after\Nthat it will terminate.
Dialogue: 0,0:50:08.67,0:50:20.00,Default,,0000,0000,0000,,That means by this time the master has read\Nthe data, then after it has read the data
Dialogue: 0,0:50:20.00,0:50:27.22,Default,,0000,0000,0000,,the master may terminate its signal, that\Nis, after this instant when the data has been
Dialogue: 0,0:50:27.22,0:50:39.30,Default,,0000,0000,0000,,read, the master will terminate its signal\Nand on seeing this, the slave may respond
Dialogue: 0,0:50:39.30,0:50:42.25,Default,,0000,0000,0000,,with a few things.
Dialogue: 0,0:50:42.25,0:50:53.15,Default,,0000,0000,0000,,Suddenly on seeing this MSYNC going negative,\Nthe SSYNC also will be pulled down by the
Dialogue: 0,0:50:53.15,0:50:56.51,Default,,0000,0000,0000,,slave.
Dialogue: 0,0:50:56.51,0:51:05.56,Default,,0000,0000,0000,,This is the indication that the slave knows\Nthat the master has performed its job of reading,
Dialogue: 0,0:51:05.56,0:51:08.63,Default,,0000,0000,0000,,now it is closing the whole show.
Dialogue: 0,0:51:08.63,0:51:16.97,Default,,0000,0000,0000,,So we say that there are two hand shake signals,\None MSYNC asserted by the master is an indication
Dialogue: 0,0:51:16.97,0:51:27.40,Default,,0000,0000,0000,,to the slave that it wants something to be\Ndone and on doing that particular work, the
Dialogue: 0,0:51:27.40,0:51:38.78,Default,,0000,0000,0000,,slave asserts the signal and on seeing the\Nassertion of SSYNC, MSYNC, the master, concludes
Dialogue: 0,0:51:38.78,0:51:50.50,Default,,0000,0000,0000,,its job of reading and then negates the MSYNC\Nand on seeing the negation of MSYNC, the slave
Dialogue: 0,0:51:50.50,0:51:52.69,Default,,0000,0000,0000,,also negates it.
Dialogue: 0,0:51:52.69,0:52:01.23,Default,,0000,0000,0000,,So we see that the signals are asserted, that\Nmeans the signals are placed and the signals
Dialogue: 0,0:52:01.23,0:52:10.67,Default,,0000,0000,0000,,are negated; that is the signals are removed\Nand you can see the specific sequence.
Dialogue: 0,0:52:10.67,0:52:17.23,Default,,0000,0000,0000,,Now there is absolutely no clock that need\Nbe used here.
Dialogue: 0,0:52:17.23,0:52:21.55,Default,,0000,0000,0000,,On seeing the signal, the other signal is\Ngenerated; on seeing the negation of this
Dialogue: 0,0:52:21.55,0:52:28.97,Default,,0000,0000,0000,,signal, the other signal is generated; and\Nin between, the required activity is done.
Dialogue: 0,0:52:28.97,0:52:36.04,Default,,0000,0000,0000,,This is the way the ASYNC bus will work and\Nyou need a set of extra signals for this.
Dialogue: 0,0:52:36.04,0:52:45.25,Default,,0000,0000,0000,,These extra signals are something like a clock\Nbecause they really do the timing, but it
Dialogue: 0,0:52:45.25,0:52:50.16,Default,,0000,0000,0000,,is not strict clock periods like this.
Dialogue: 0,0:52:50.16,0:52:56.65,Default,,0000,0000,0000,,So generally these are timing signals; that\Nis about the synchronization.
Dialogue: 0,0:52:56.65,0:53:54.99,Default,,0000,0000,0000,,We will see more about these processes in\Nthe next lecture.