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35c3 pre-roll music
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Herald: The next talk is the talk on
LibreSilicon project that's meant to
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create a free and open silicon
manufacturing process. And our speakers
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today are leviathan, chipforge and
Andreas Westerwick, creators of
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LibreSilicon. So let's give them a firm
round of applause and please welcome them.
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applause
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David: Oh, it works, ok. That's problem.
That's what essentially is all this fuss
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about is actually a description of how
we... what this waver means and where we
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will go with it. And yeah, I give now
already over to Hagen which already starts
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elaborating on the basic conceptional
things.
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Hagen: OK. Hello everybody. Hope you have
a fresh mind. It could be heavy. OK. Let's
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start. What we are. Last year David was
involved at the project to looking for
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free silicon, just a way to manufacture
his own chips and figured out it's
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difficult. You need a lot of contracts for
that, NDAs (non-disclosure agreements). So
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he looked around and find a clean room. We
had to come in and say, OK, we can rent
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it. Then he entered a scene on the last
Congress - a lightning talk - and said, I
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like to do that. And I wasn't in the
auditorium there, but a guy told me later,
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OK, look at this lightning talk. It's very
interesting. You'd already doing chips. So
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I entered in sees it or seen the talk
recording and see it. Nice idea, I will do
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that too. And the whole year we meet us by
mumble. It's just a thing of distance you
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know. David is located in Hong Kong. The
clean room is there. And I worked from
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Germany. So we exchanged e-mails. We
talked on a mailing list. We built up a
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small community for that and we had a
first hackathon just to figure it out,
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what we are doing with the tools, which
tools are available how we can use them,
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are they usable at all or not. And this
was in May and during the process the
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group wised up and already two of us got
their qualification to enter the clean
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room. The Hong Kong University is a
little bit strict in that. You have to sit
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there in the courses, you have to do exams
and if you're fine with the exam then you
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get the permissions to go in. So Victor
which is on the most left and David on
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the most right, they have the
qualification for that and they
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manufacture our wafer which you have seen
there. It's a small one, but it's the
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first stuff we have, right? OK. The basic
points, what we are doing. We are using
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a quite, let's see, old technologies from
the 80s. It's one micrometer feature size.
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It means a gate length of the transistor
has one micron. It's not comparable with
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all the processors you can buy now. It's
quite old, it's really stuff from the 80s.
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But we do it in a new way. We don't use
the technology from the 80s. We do it with
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the knowledge and all the experience from
newer technology. Doing it again and using
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some steps which are not so common, well,
it wasn't common in the 80s. So why one
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micron? One micron also means that the
transistors are very robust against five
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volt. Five volt was a usual supply voltage
in the 80s, 90s and something like that.
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Now the supply voltage is going down,
down to less than one volt but for
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tinkerers, for hobbyists, for makers, it's
a nice value because older stuff, many
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boards are still working with five volts
and we're able to handle this voltage. So
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we have a twin-well process; usually in
the 80s there was just one well. OK, we
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have to hurry up. We have three metal
layers. We have interesting additions and
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we are suitable for low tech. Ghetto tech,
I would say. You can use it without
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sophisticated equipment. We can analog
stuff and so on and analog stuff means you
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don't need small structures. OK. Areas
where we have to work on. First, the
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process. It's almost done. You have
figured out it works with measuring. OK,
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the next stuff: we need the tools. But the
tools are also very old and mostly not
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usable. We have to deal with that stuff.
We have to rethink the tooling for that
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and we need standard cells. That's my
task. OK, so a couple of thoughts about
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standard cells. They are very common.
Usually, if you have a need to translate
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your Verilog or VHDL and to bring it on a
silicon you need small gates. NAND gates,
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OR gates and so on. But these gates need a
lot of representation, the combinatorial
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sequencing. So OK. These are typical
cells. Just a couple of them. But imagine,
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we need much much more and there's design
goals for the standard cells as we need
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almost complete possibilities. If you have
just this small selection of cells, the
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netlist becomes huge and every gate in the
netlist also means a dedicated delay. If
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you have long chains we have a long delay
so that our operating frequency goes down.
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So if you have more complex gates we are
better but doing all this stuff is heavy,
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but we like to be lower power. That means
our cells have to be consumption less
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power than usual. We want to be fast but
yes, of course, it doesn't fit all
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together. OK. So we need it for
simulation. We need it for synthesis. We
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need it for timing. As you can see
everywhere on the slides and, of course,
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documentation. That's a lot of work. We
are a small team. I am the only guy who is
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dealing with the standard cells it's
usually our teams also are doing that. So
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OK, we need a tool for that which does all
the stuff for us. And this cell generator,
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I called it popcorn, because I put in some
corn and it rised up with the heat. So we
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can get all the representation. So
currently I have this tool on the
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repository which is Tcl which does some
stuff I like, I need, but not all. But it
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already seems very ugly. So for me I like
to rewrite that but I don't figure out
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currently which language I like to use for
that. Next time it could be rust, it could
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be scheme or something like that. We need
another language for that. So if someone
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would help - please, but that's the next
task, if you have the wafer done
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completely and measured. OK. That's a link
for the repository where you can look at
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the current status and there's a wiki
where I like to describe why I'm doing
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what in which way. But yes, we have to do
a lot more. OK.
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Andreas: OK. Hi. I take a look at the
current tooling that exists like
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layouting, place and route to minimize the
yield on the wafer. And obviously because
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this is the LibreSilicon project we look
at open source tools. So we have Yosys and
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graywolf, qrouter and several other FPGA
routers that exist. Yosys is pretty good.
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We can probably use this for the
synthesis. But the other tools, they lack
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very critical qualities for this... for
silicon because they, for example, they
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are part of qflow which is an FPGA
workflow. So the graywolf tool, it
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originates in academia. It's, like, it's
many decades old. It comes with some very
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good ideas, for example simulated
annealing which is a meta-heuristic
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you can use to solve NP-hard problems, but
it's only one of the many choices you can
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make to solve the extra hard problems. But
it also comes with bad implementation, for
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example inline syscalls is a very bad
idea. And it's also written in C and blah
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blah, OK. Qrouter is actually... it's
pretty good. It started in 2011 by Tim
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Edwards. It's widely used for, by hobbyists
and enthusiasts to route for FPGAs. But
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it's not ready for silicon and it's
especially not ready for our LibreSilicon
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process which would require us to to write
a lot of C code for Qrouter. Also
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parallelism apparently is not in scope, so
I mean if we want to scale up, for example
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place and route in the cloud or whatever or
use modern CPU architectures, we are stuck
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with sequential routing which is pretty
bad. Also it lacks a very important
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aspect, in my opinion, which is formal
correctness. So when we produce wafers in
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the fab we want to make sure that they
don't blow up in our faces. This is why we
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need some form of proof that our
algorithms are correct and therefore the
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result is correct. There are also other
productive tools that are proprietary
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where we can look at, but we cannot use it
or fork it or whatever but we can learn
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from the research that has been done, for
example BonnRoute. BonnRoute is used by
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IBM. The Cadence suite, I believe, is used
by Intel and the Alliance tools is French
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academia. Very UNIXy, I mean it's a very
it's a very large set of small tools that
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convert different file formats to another.
I mean, maybe you encountered this problem
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before when you did some hardware design;
you have many different file formats that
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all don't play together very well. So you
have tools like X to Y which convert file
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format x to y. And you see when you want
to place and route and layout a very very
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large chip, like a Very Large Silicon
Integration, then this isn't even done,
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like, automatically by tools. This is done
with manpower. When you look at a very
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large chip done by Intel or IBM. So this
is an example of a very very large chip as
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you can see. I mean do you think this has
been done by automation like industry 5.0?
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No. This is all manpower and a lot
of manpower. Which we don't have, The
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LibreSilicon project at the moment. So
this is the state of the art is like
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okay the manpower thing is one aspect but
the other thing is so what you do is
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you do placing and routing at different
steps at the design process so you do
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placing for a very large chip, floor
planning and then you do a global routing
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which is you /can imagine it like
routing along a rough chessboard. And
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after that you do a very detailed
routing where all the different
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constraints regarding your technology come
into play and so again the formal
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correctness aspect. So you have some
imperative algorithm that you cannot prove
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will blow up. And it's also not a very
parallel code. So you're still stuck with
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the sequential nature of the code and you
have no parallelism. What we propose is to
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not place and route for large chip but
to decompose the large chip into much
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smaller units like a component hierarchy
or a sub cell hierarchy and then place and
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route the small chips at the same time and
then reuse the small units in larger
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units. So you get an evaluation tree you
can work on and compile just the
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components you need. Also we propose
satisfiability modulo theory solvers so we
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can have some first order logic where we
can have constraints on the components,
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how they are placed for example they
don't - they must not overlap.
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Let's take the most simple example I will
show you like later. And also we want to
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achieve parallel or declarative code. So
as you can see we have some, we have many
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disagreements with academia and industry
which work very well together for example
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when you want to study semiconductor
design you have to sign some NDAs with IBM
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or Intel to do that. So, they say
placement and routing or floor planning
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and routing are different problems and
they need to be solved at different times
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in the process. And then all the
components can be registers or NAND gates
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it does matter they all treated the same.
No it only matters that uh the floor
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planning stand first and then the routing
the closed routing then a detailed
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routing. What we propose is that place
and route is actually the same problem and
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that registers are different from full
adders. Okay. So the geographical
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partitioning of a wafer is called floor
planning or the placing step. And this
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results in a cut tree. So this is how they
do routing hierarchies. They just divide
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the wafer into smaller pieces and then do
the following steps based on this
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placement. What we want to do is have
subcell hierarchies and those sub cells
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they are either explicit like they are
explicitly developed for example the
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rocket ship is very modular and it has
many explicit verilog modules you can use
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and place and route that and then reuse
it. And it also has implicit sub cells like
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for example most of the time. For example
you have a full adder it obviously is
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composed of one bit adders so you can
place and route one bit adder and then
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place and route based on the one bit
adders that you artfully placed and routed.
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And as a result you get a full adder.
That's just one example but I will show
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you a tree, a few slides. So there you see
parallelism. There's something very
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important for us. BonnRoute allocates a
lot of research to have some mathematical
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model for concurrency and shared memory
models. qrouter, which is the open source
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alternative, has none. I mean that's
apparently not in scope. And what I
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propose for the LibreSilicon compiler is
the map and reduce approach. And as I've
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mentioned you get explicit subcell
hierarchies through high modularization.
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That is done by the developers and
you also get implicit subcell hierarchies
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by compression-like algorithms that exline
as opposed to inline the registers or one
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bit adders. And this is also about
preserving these newfound hierarchies in
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the compiler interfaces so you don't end
up inlining them again because this is
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not a Von Neumann architecture where it
would make sense to inline a lot of code.
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So the code runs on the stack and the
level 1 cache. This is about reusing
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components. Okay. So this is a part of the
rocket ship, the system bus is one
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component of a very modular chip rocket
ship. And as you can see it is composed of
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several simple lazy modules and those
simple modules are again composed of other
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components. And then you have a lot of
queues and this number on the left says
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how many times it's been used. For example
queue 15 is used 5 times in the
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AXI4Deinterleaver and this is only the
explicit hierarchy that is declared by the
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developer. Okay. Now when you apply some
compression-like algorithms you can
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actually gain, you can get more leaves so
you can be even more modular. For example
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queue 1 is composed of several implicit
modules and you can see one queue is even
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reused seven times. So you just route,
place and route these green leaves like
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once and then you can reuse it in the
queue 1 and everywhere where queue 1 is
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reused some at some other point in the
chip. Now I want to state a very simple
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optimization problem. What we need for
the process is to have components and
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wires that connect the components or nets
and these nets and components are actually
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rectilinear geometries, the components
shall not overlap and the nets shall
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overlap with the respective pins they are
supposed to connect. The minimizing goals
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of this optimization problem is layout
area, which is the most critical one
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because this is what maximizes yield, the
maximum wire length because it's about
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resistance, the wire count you want to
keep very small but you want to allow for
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wires. The crossing number is a
computational thing. It doesn't really
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matter for the implementation on the
silicon and you also want maybe you want
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to minimize the wire jogs which is bends
in the wire. So to to solve optimization
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problems in 2018 maybe you want to use an
abstraction from the SAT solvers. You used
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to know academia came up with some pretty
neat theory is called satisfiability
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modulo theories and you can just put some
first order logic and give it to a solver.
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I've listed a few. For example ABC is used
by Yosys and Z3 from Microsoft, also very
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promising product, but you can obviously
choose from many products by academia and
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industry. Just a quick reminder what
boolean satisfiability is: find
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assignments for all these six variables
which are boolean so that the whole term
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is true. And now with SMT or
satisfiability modulo theories you can do
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the same thing but now with integers and
also more complex data types but integers
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are the most interesting. So let's do
something with SMT. For example we have a
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component that is rectangular. And now you
can see this is like a Cartesian
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coordinate system and you have the left
bottom point which is x and y and then you
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have the right and the top point. And now
if you for example have this problem that
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you don't want to have overlapping
rectangles you can have a rectangle A and
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rectangle B and declare these coordinates
and then have some proposition that shall
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be true and to have a proposition that
says they shall not overlap is to say
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this. I mean it's actually the lower half
that makes sure that they don't overlap
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and the upper half makes sure that the
components actually have the right
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dimensions. Well in this example they
obviously have the same dimensions the
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same components. And so you make sure
that the left point of the second
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rectangle is right of the... Okay no,
never mind. One last important point I
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want to make is that this this framework
we want to create, it's not based on the
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inheritance model that we've seen in the
process steps right now. But we want to
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combine the problems. For example the
overlapping problem, the pin connect
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problem, and then arbitrary constraints
that come up during the process
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development that Dave and Hagen will
supply me with and I will formulate that
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in first order logic. And then this
makes sure it's formally correct and it
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doesn't blow up. And as you can tell I
mean I've combined many NP-hard
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problems at the same time but I think we
can manage that if we have very small
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cells so I'd suggest we just stay here and
don't do all this for very large chips but
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reuse small chips and then reuse the small
chips in other small chips. The silicon
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compiler is one half of maximizing
yields. And the other half is to get the
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process right so to get the process right,
we have David and Victor. So please.
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David: So thanks for the handover. So very
first. There's a lot of questions why Hong
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Kong. So one thing why this is a
really suitable place to do that is
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because of history like the epic Commodore
64 has been made in Hong Kong. Then the
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chips in the first Macintosh have been
made in Hong Kong and all of these
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manufacturing lines. Some of them at least
one is still available. So also there is a
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very advanced laboratory. That's the NFF,
Nano Fabrication Facility in
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Clearwater Bay and they let us kindly use
their equipment to develop this process.
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Also one of the sectors I mentioned
before, RCL semiconductors, they're really
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open to introduce LibreSilicon in their
mass-manufacturing lines: one in Shenzen,
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one in Tai Po. So in conclusion of that we
have advanced R&D labs there. There is
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factories available. We can easily export
it to here over channels which already
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exist. Right. And also in general it's
just more relaxed over there. And I don't
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like minus degrees. So our process is a
little bit of a monster. So it makes sense
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to tackle that one by one so we are right
now feeling ourselves upwards to get the
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standard CMOS debugged, final with
optimized frequencies there. But we
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already have on the Pearl River, I've shown
you, we already have test structures for
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high voltage MOSFETS, B junction
transistors, Zener diodes, even flash,
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resistors, and caps. So it's only a
question of effort I guess in the next few
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months to get that working. When we
designed the process like, how it usually
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works when you make a process, you look at
the machines you have availlable, what can
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these machines do, optimum operation range
and then you look what substrate, what
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material you have available and then you
start tinkering you own little proprietary
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process. That's how fabs do that. And we
said, OK, well, to the point where we look
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at the machines - what can they do? We
do the same, but afterwards we look that
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it's portable. Not specific to the
equipment. So just because we have certain
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machines which can do awesome things, but
are really exotic, doesn't mean we have to
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use them. So we avoid exalting machines so
that it's as portable as possible. And we
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also try to use wet etching whenever
possible in order to make sure that you
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even can build it in a basement. And here
Evan Heisenberg may be interested now in,
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you know, changing business into a less
dangerous business. And, yeah, they can't
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be leading the innovation hub Hamburg I've
seen, like this improvised clean room with
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just a diffusion furnace. So, that's a
cross-section of the... it's not
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finalised, but you see a cross section
theoretical that's... by the way, you can
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find it on GitHub as well. It's all in the
publications, everything we develop, all
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the measurement data, all this on GitHub.
So that's actually the layout of these
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little squares here on the wafer. You
see the apple in the middle. It's just in
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this year. That's, uh, it's nice. I have a
Python script in the GDS2 generator
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tool folder for Python and you
can take any png or anything and just
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convert it into layout format, so you can
put your own pictures onto the metal free
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layer. So in case you already have
interest into making little trips also.
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It's also possible to make, like, ear
rings also with ... We don't care as long
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as there are 4 more millimeters on the
silicon. You can put pictures on the
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silicon. So that was the Pearl River
right. And the Pearl River fulfills the
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function for us at the moment to debug all
the features of this LibreSilicon process.
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Then the next thing we have to use it to
calibrate new foundries so now, we
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developed it at the NFF in Clearwater Bay
right. And afterwards we go over to HQ
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with, to the RCL guys in Tai Po, and they
have the machines and then we have to pipe
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the Pearl River layout through there as
well and repeat that process over and over
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again until the measurement data, like
the frequent, the you know the Beta
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depending on Omega of the transistors and
the resistance of the wires and everything
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kind of is the same as at NFF so that you
can basically, as I mentioned before one
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of the design concerns is portability
that you can basically prototype a chip
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at the NFF and then produce it in RCL or
in maybe some other fab in Shenzhen or
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whatever. And so and if there are new
features coming out which also make a new
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release of the Pearl River test waver and
we give that around they push it to GitHub
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and people can introduce and calibrate the
process to support the new feature. And so
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that's how does that work. So usually,
typically you have something like a photo
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mask like here. I didn't bring that one
because it's in a clean room there and the
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dust might scratch my micro structures on
there. So also afterwards I have to clean
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it for half an hour and when I come back
to Hong Kong from here I'm so jetlagged I
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just want to get started again, not wait
for the mask.
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But there's a picture.
And these masks,
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usually a stepper/aligner specific. If you
don't have a stepper then you need to make
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a direct transfer that means you actually
have to put the chips in the size you
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want to expose them directly onto the
mask. Then press the mask onto the
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00:35:00,459 --> 00:35:05,510
photoresist, expose and develop. That's
messy because you have to clean the mask
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all the time. And it really depends. So
actually you can do exposure even without
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a stepper. So we actually really could do
it also there in this university lab in
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00:35:15,029 --> 00:35:24,440
Hamburg. So all you need is a new UV
light. laugs So we have a little bit more
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00:35:24,440 --> 00:35:33,019
advanced tech in Hong Kong. So we have
here an SVG coater, this baby dispenses
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automatically HPR 504, a resist. So we
actually just have to put in the left, you
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see the cassette slot. So you put there
like twenty five wavers or so and then you
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have a receive slot and put another
cassette there and it just starts sucking
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in the wafers one by one, puts primer on
it, soft bakes it, and easy. Then you
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expose it, develop it, hard bake it,
chilled. We have two types of resist actually
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and the 6400L for the implantation
unfortunately has to be put in manually.
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So it comes and it gives you 10 seconds
to open the chamber and put the resist on
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it. In both cases however it doesn't
really matter so much because the
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thickness of the resist is depending on
the RPMs of the spin coating unit. So you
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just have to kind of put two thirds of the
waver should be somehow covered with the
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resist and the excess resist goes away.
But you have to control the RPMs because
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depending on when you do wet etching for
instance and HPR 504 has to be enough
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thick because of selectivity, so that you
don't etch and consume the polymer,
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the resist. So you have to make it thick enough
that you don't have,
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you haven't consumed all the polymer before
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you have etched your structures. And the
same goes for the implantation because you
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need 6400L, this one can sustain higher
temperatures so you can use an implanter.
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Now afterwards after exposure development
it looks like that. That's an alignment
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cross for our optical stepper and for
instance that's our ring oscillator. So
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it's one of the structures on our Pearl
River actually. So N well, P well. I have
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00:38:07,020 --> 00:38:11,500
to hurry up, only 10 minutes or so. So
that's a picture of the developing we have
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00:38:11,500 --> 00:38:16,269
some P well mask developed so we have
everywhere resist except in this little
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00:38:16,269 --> 00:38:22,739
crosses and stripes there. That's there
below is the silicon where we implant. The
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00:38:22,739 --> 00:38:32,789
recipe is easy, first coat, expose the
implant and then resist strip. Same for
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00:38:32,789 --> 00:38:41,480
the P well and after the resist strip you
can put it into a diffusion furnace in
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00:38:41,480 --> 00:38:48,809
the atmosphere for like four hours. So
where does the four hours come from? So
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we have the Fick's equation. And the
Fick's equation is essentially in a
318
00:38:54,190 --> 00:39:00,760
similar shape like the laplace heat
conduction equation, so to solve, there
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00:39:00,760 --> 00:39:07,079
are already nice solutions for it. So for
instance if you use boron or phosphorus
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00:39:07,079 --> 00:39:13,200
which has the nice property that they have
the same constants for this Dₑ. So if you
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have the same temperature you basically
have the same Dₑ for phosphorus and boron
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00:39:18,859 --> 00:39:23,770
so you can implant them next to each
other and then put them at once into the
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00:39:23,770 --> 00:39:29,690
diffusion furnace and the wells are the
same depth. So that's why these two
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00:39:29,690 --> 00:39:36,630
materials are usually used for diffusion.
So that's one of the solutions that you
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00:39:36,630 --> 00:39:44,670
get, the surface for doping for the
threshold equation which I also will rush
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00:39:44,670 --> 00:39:53,150
through in a moment as well. The
equations you see here with background
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00:39:53,150 --> 00:40:02,080
doping it's a little bit much. As you have
here this natural logarithm inside. But
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00:40:02,080 --> 00:40:07,539
besides that you see this jump and that's
how you essentially build a well, you have
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00:40:07,539 --> 00:40:13,609
the background doping and you compensate
the donors and acceptors with each other
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00:40:13,609 --> 00:40:22,359
so that's what this absolute value of the
difference means. So the threshold
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00:40:22,359 --> 00:40:27,789
equation is pretty easy. And like
basically mirrored for PMOS and NMOS that
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00:40:27,789 --> 00:40:33,039
just like mirrored in the sense that one
of the transistors as PMOS is built on a N
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00:40:33,039 --> 00:40:47,069
well and NMOS is built on a P well. Right.
And what essentially controls the
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00:40:47,069 --> 00:40:50,930
threshold voltage, so the operational
voltage, which usually in the standard
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00:40:50,930 --> 00:40:59,400
CMOS is around 0.8 respectively minus
0.8. That's doping here like the donars
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00:40:59,400 --> 00:41:07,709
respectively acceptors and the q as
usually that's the oxide charge. This is
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00:41:07,709 --> 00:41:16,069
usually a process specific constant but
that can change. And then you get
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00:41:16,069 --> 00:41:21,709
flash, it can change Q_SS and then
it's flash. That's what you use in SONOS
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00:41:21,709 --> 00:41:29,469
flash, stands for silicon oxide nitride
oxide silicon. So there you have a
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00:41:29,469 --> 00:41:38,680
standard again, NMOS in this case but you
have a sandwich instead of a normal oxide
341
00:41:38,680 --> 00:41:44,559
layer and for the gate oxide you have a
nitride and oxide. These oxide layers
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above and below the nitrate are called
tunnel oxides. And the trick is that with
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high enough energy you tunnel electrons
into the, through the oxide into the
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00:41:58,959 --> 00:42:04,099
nitride where it's trapped and then you
shift the operation voltage, the threshold
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of the transistor. And when you then put
one at it it doesn't turn on anymore and
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that's essentially how the most used flash
solution besides normal floating gate
347
00:42:18,999 --> 00:42:27,759
works. It's really simple. So. And after
you get your wells out of the furnace, so
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I did a little detour. You want to make
sure that the lateral diodes which got
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into existence after diffusion don't
create unwanted short circuits. So we use
350
00:42:41,440 --> 00:42:46,549
the technology actually developed much
later after one micron already has been
351
00:42:46,549 --> 00:42:52,559
out. It's called STI shallow trench
isolation. It's from the ULSI technology
352
00:42:52,559 --> 00:42:59,019
as well as the silicide we use to reduce
the resistance of the polysilicate.
353
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Here are some pictures, we did etch this
one in the lab. That's the islands so that
354
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around everything going down that's the
trenches in between the gates and between
355
00:43:14,160 --> 00:43:23,500
the wells. So we isolate them from each
other. So the recipe is pretty easy.
356
00:43:23,500 --> 00:43:26,729
So either you have a plasma
etcher around or if you're not
357
00:43:26,729 --> 00:43:31,640
rich and don't have money to buy a plasma
etcher from eBay you can also get this
358
00:43:31,640 --> 00:43:43,339
tetramethylammonium hydroxide. And it's
not even the german name, so cool, and
359
00:43:43,339 --> 00:43:52,369
dilute it with deionized water 3:1 and
this 25% TMAH solution you heat
360
00:43:52,369 --> 00:43:57,780
it up to 80°C, dip your
wafer in for six minutes and then you
361
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would get your structures. Metal is
easier. So we did here the metal
362
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interconnect for the ring oscillator.
They're etching it, also you make a
363
00:44:12,309 --> 00:44:18,809
vacuum, deposit 100 nanometres aluminum,
30 nanometers titanium for passivation.
364
00:44:18,809 --> 00:44:23,589
Take the vacuum away dip it into HF until
you don't see streaks on the titanium,
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00:44:23,589 --> 00:44:28,250
then into aluminum etchant until you don't
see streaks from the aluminum. And then
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you have your wires. I'll skip
that one. That's just really interconnect.
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But I plan to make videos soon where I go
through the you know like daily video blog
368
00:44:44,640 --> 00:44:49,539
of results but just that you see that you
see the oxide depending on the angle it
369
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has different colors. So that's L2 the
isolation. And then you see the
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topological measurement device. You see
this one micron because we only deposited
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a micron for now. You'll see the heights
the differences and we see that one micron
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is not enough. So we'd still have these
sharp edges which we don't want. So we have
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back in Hong Kong have to deposit another
2 microns. And if you want a follow up you
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go to my Github. OK? So Victor that's him
and I have done that so far. It's only
375
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like two weeks because it took a lot of
time to get all the masks manufactured and
376
00:45:36,699 --> 00:45:41,789
so a lot of bureaucracy. We already have
that much and just stay tuned. We already
377
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have figured out so much in the last two
weeks that it shouldn't be long before we
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00:45:46,819 --> 00:45:57,779
can well finish all the features of Pearl
River. Create models with Hawkins popcorn
379
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and start figuring out all the analog
stuff for our MCU and then we make
380
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an MCU. That's the first thing we want to
do as soon as we have the features figured
381
00:46:07,219 --> 00:46:17,409
out of Pearl River. If the Goddess is nice
to us. Yeah it's a discordia figurine,
382
00:46:17,409 --> 00:46:23,319
it's really cheap on ebay. laugs
So yeah. And that's like an overall
383
00:46:23,319 --> 00:46:30,700
of the features. And we want them build
this microcontroller, and yes because all
384
00:46:30,700 --> 00:46:34,279
the folks don't believe that there are
people who want to buy such items you
385
00:46:34,279 --> 00:46:45,319
please fill out the survey. That one
is from Hagens trip, i skipped it but
386
00:46:45,319 --> 00:46:50,380
yeah. So yeah. Thanks. I'm done. And too
late but sorry.
387
00:46:50,380 --> 00:47:00,900
applause
388
00:47:00,900 --> 00:47:05,770
Herald: Thank you for the talk. No, but if
you wait we have time for questions. So
389
00:47:05,770 --> 00:47:10,770
there are two microphones. One is in the
middle and one is on the left side of the
390
00:47:10,770 --> 00:47:16,410
stage. Line up and we're going to take
some questions and there is already one
391
00:47:16,410 --> 00:47:23,269
question from Microphone number two.
Microphone 2: OK. So thank you for that
392
00:47:23,269 --> 00:47:28,700
interesting talk and all the development
that you're doing. I was wondering have
393
00:47:28,700 --> 00:47:37,900
you had any time to test your transistors
yet. And then later on do you plan to
394
00:47:37,900 --> 00:47:42,852
release some sort of analog simulation
capabilities.
395
00:47:42,852 --> 00:47:48,709
David: Yes. Thats the plan for the next
few weeks after I'm back in Hongkong. We
396
00:47:48,709 --> 00:47:53,329
did go back to the cleanroom. We actually
wanted to provide already something for the
397
00:47:53,329 --> 00:48:00,669
Congress. Unfortunately we were noticed,
short noticed that Thursday and Friday
398
00:48:00,669 --> 00:48:06,289
they take the wet stations and the
machines offline for maintenance of the
399
00:48:06,289 --> 00:48:13,140
AC. So we have already like, the wafer, we
have the isolation oxides but we didn't
400
00:48:13,140 --> 00:48:19,119
have any time left to actually test the
the you know only having polysilicon is
401
00:48:19,119 --> 00:48:22,730
not enough. You have to also have metal to
go with probes there, that stuff is
402
00:48:22,730 --> 00:48:27,279
micron size.
Hagen: Okay. So your question as I
403
00:48:27,279 --> 00:48:31,730
understand was in the direction of
simulation right? We like to measure all
404
00:48:31,730 --> 00:48:38,279
the structures we have to produce and with
the values we get we like to feed in spice
405
00:48:38,279 --> 00:48:45,789
models. So you can do analog simulations.
And yes we like to use this technology for
406
00:48:45,789 --> 00:48:50,369
analog stuff because as I already
mentioned one micron size is enough for
407
00:48:50,369 --> 00:48:56,279
analog. You don't need smaller structures.
Analog all this having huge transistor
408
00:48:56,279 --> 00:49:03,849
size from 20 or 50 Microns. So they
are huge, you don't need this small
409
00:49:03,849 --> 00:49:11,349
technology. So they are quite feasible for
analog stuff but let's say in this way if
410
00:49:11,349 --> 00:49:16,150
you're doing analog stuff in a
conventional way you have to sign all the
411
00:49:16,150 --> 00:49:21,259
NDAs and you're stuck on this technology
you're using. You can't transfer your
412
00:49:21,259 --> 00:49:27,170
design to the next fab because in the next
fab the PDKs are different. You have to
413
00:49:27,170 --> 00:49:31,380
transfer or to translate all the
structures there for a rebuild again for
414
00:49:31,380 --> 00:49:36,250
the new technology if you have a
technology which you can take from one fab
415
00:49:36,250 --> 00:49:42,720
to another like our one. You are quite
happy because the analog stuff you
416
00:49:42,720 --> 00:49:49,400
designed once also fits for the next fab.
So yes of course we like to support analog
417
00:49:49,400 --> 00:49:54,529
stuff. We need help for that of course we
have to measure, we are currently
418
00:49:54,529 --> 00:49:58,150
developing the wafer, we are currently
working on the documents how to measure,
419
00:49:58,150 --> 00:50:02,799
what we like to measure and then we have
to transfer the values to spice. But we
420
00:50:02,799 --> 00:50:08,799
have documented how we are doing that.
And so everyone can use the knowledge.
421
00:50:08,799 --> 00:50:12,209
Mic 2: Thank you.
Herald: Thank you. Mike one please.
422
00:50:12,209 --> 00:50:17,069
Mic 1: Do you have any plans for
open source mask production like.
423
00:50:17,069 --> 00:50:25,920
David: Yes. Actually the problem is only
that as I mentioned before. If you want to
424
00:50:25,920 --> 00:50:30,390
have an opto mask for steppers that's
always manufacturer specific. If you want
425
00:50:30,390 --> 00:50:37,529
to have a direct transfer mask not a
problem. So I guess so Sam is really
426
00:50:37,529 --> 00:50:44,680
helpful in the lab. He runs the laser
scriber. We could talk with the folks at
427
00:50:44,680 --> 00:50:51,499
NFF. They were really lovely helpful
really. They really like to really help us
428
00:50:51,499 --> 00:50:58,959
a lot. And now that we talk with RCL.
They also have laser scribers that we could
429
00:50:58,959 --> 00:51:04,660
actually also start producing masks in the
long run. So yes that's certainly one of
430
00:51:04,660 --> 00:51:13,150
the things I intend to do is providing
optical masks for exposure. Um yeah.
431
00:51:13,150 --> 00:51:17,180
Herald: Thank you. Uh one more question
from microphone two.
432
00:51:17,180 --> 00:51:25,009
Mic 2: Great talk thanks. I'm really
interested in the - what it would take to
433
00:51:25,009 --> 00:51:31,039
build the fab. What's the minimum set
of tools. We've already seen a couple of
434
00:51:31,039 --> 00:51:37,559
orders of cost reduction in, through DIY
bio hacking by making the tooling a lot
435
00:51:37,559 --> 00:51:44,299
cheaper. Do you see that happening within
the nearest decades and your sort of work?
436
00:51:44,299 --> 00:51:51,250
David: Yes. So for instance I made my
process by purpose this way that you can
437
00:51:51,250 --> 00:51:56,640
actually improvise most of it like the LTL
growing and deposition and everything with
438
00:51:56,640 --> 00:52:02,390
a furnace. So what you need is a wet
etcher like some wet etch station. You can
439
00:52:02,390 --> 00:52:08,200
actually there is a video from Jeri
Ellsworth called "making microchips
440
00:52:08,200 --> 00:52:16,210
at home cooking with Jeri" and he does
microchips in the kitchen so it's
441
00:52:16,210 --> 00:52:21,489
not, you get scared like HFS, it dissolves
your bones and so on and then you see the
442
00:52:21,489 --> 00:52:25,390
guys who already have qualified, are
qualified or employed there: they just
443
00:52:25,390 --> 00:52:33,739
without any PPE, nothing just grab into
the HF. That's just the skill to scare
444
00:52:33,739 --> 00:52:40,509
folks from generating insurance problems.
In general it's not really that dangerous
445
00:52:40,509 --> 00:52:48,069
right. You can do the stuff at home. No
problem. Yeah. So we intend. So this
446
00:52:48,069 --> 00:52:55,999
process I made is so trivial. So we have
also a branch called super low tech. We
447
00:52:55,999 --> 00:53:02,039
just shall essentially but it's more RnD.
But you could actually help there for
448
00:53:02,039 --> 00:53:08,150
instance figure out the last details,
get a furnace from eBay put it onto your
449
00:53:08,150 --> 00:53:17,410
kitchen table start RnD-ing make some git
pull requests and we're super happy. Okay.
450
00:53:17,410 --> 00:53:22,109
So it's doable and the furnace you get on
ebay. So no problem.
451
00:53:22,109 --> 00:53:29,559
Herald: Thank you. Microphone 1 again.
Mic 1: So you just said about the
452
00:53:29,559 --> 00:53:33,660
analog stuff that a lot of that is usually
under NDA from the fab. So have you
453
00:53:33,660 --> 00:53:38,509
encountered any problems with the fab and
that you're currently using in that you're
454
00:53:38,509 --> 00:53:43,789
actually trying to discover these
processes for yourself like you're
455
00:53:43,789 --> 00:53:48,089
generating competition that they might not
like, have you had any problems with that.
456
00:53:48,089 --> 00:53:54,939
David: Oh no I had a nice phone calls,
e-mails with the owner of the fab over in
457
00:53:54,939 --> 00:54:01,960
Tai Po who also has a second branch in
Shenzhen that's RCL. I actually asked him
458
00:54:01,960 --> 00:54:08,109
recently "Hey is it okay when I use your
logo in the presentation and implicitly
459
00:54:08,109 --> 00:54:13,319
make an advertisement for your fab here?"
No prob go ahead. That is like...
460
00:54:13,319 --> 00:54:18,579
He's really eager to, LibreSilicon
is what they need because every fab
461
00:54:18,579 --> 00:54:24,269
usually has to invest money in to develop
it. First they develop a proprietary
462
00:54:24,269 --> 00:54:30,069
process right, or they license some
proprietary process from another company
463
00:54:30,069 --> 00:54:38,260
and then they have to invest RnD costs to
develop IP cores for their setup. With
464
00:54:38,260 --> 00:54:43,920
LibreSilicon the problem is solved for
the companies because these foundry is
465
00:54:43,920 --> 00:54:49,099
using LibreSilicon everything the
community develops is on github. And
466
00:54:49,099 --> 00:54:55,689
that's the IP catalog essentially.
So they don't have to invest any
467
00:54:55,689 --> 00:55:00,380
additional money into RnD-ing IP cores
that's in the nature of open source that
468
00:55:00,380 --> 00:55:05,799
there are IP cores popping into existence
all the time. They can focus on the thing
469
00:55:05,799 --> 00:55:10,940
they're best at: making silicon, right? So
it's actually positive but only for the
470
00:55:10,940 --> 00:55:15,579
small foundries that are really interested
especially Shenzhen and now some in India
471
00:55:15,579 --> 00:55:22,420
and some of the big foundries and they
will not, they are anyway the big
472
00:55:22,420 --> 00:55:27,089
companies have the tendency to be as
mobile as a cargo ship. So it will take at
473
00:55:27,089 --> 00:55:32,069
least like two years until they
acknowledge that LibreSilicon exists and
474
00:55:32,069 --> 00:55:39,869
then we might expect some legal you know
bullying. But for now they won't even they
475
00:55:39,869 --> 00:55:46,390
just laugh right. They just laugh at best.
476
00:55:46,390 --> 00:55:49,819
Herald: We're going to have two more
questions before we're out of time.
477
00:55:49,819 --> 00:55:54,459
Microphone 2.
Mic 2: Why did you go for the twin well
478
00:55:54,459 --> 00:55:57,650
process as opposed to the simpler single
well?
479
00:55:57,650 --> 00:56:02,180
David: Uhm that's a good point. That's
also something with portability and if you
480
00:56:02,180 --> 00:56:06,769
have different events or different
supplier for substrate it might be that in
481
00:56:06,769 --> 00:56:13,559
n-doped or un-doped substrate. So with
twin well architecture and actually we
482
00:56:13,559 --> 00:56:18,360
have on the n-well we also built p-bases
and in these n-bases, so we have actually
483
00:56:18,360 --> 00:56:27,519
like stacked wells in the n-wells and
p-wells. So actually it's a one two. Um
484
00:56:27,519 --> 00:56:35,969
Pentagon Well I don't know. Um and it's
just that you can shift to
485
00:56:35,969 --> 00:56:42,819
the doping of the n- and the p-substrate.
According that you fit LibreSilicon
486
00:56:42,819 --> 00:56:48,259
requirements to still have the physical
properties ensured by LibreSilicon. No
487
00:56:48,259 --> 00:56:53,009
matter whether you get your substrate from
somewhere from Great Britain or from
488
00:56:53,009 --> 00:57:01,160
TaoBao.
Hagen: Okay. The thing is we looked before
489
00:57:01,160 --> 00:57:09,349
at eBay which wafer we can get. Currently
NFF is supporting us with wafers. But if
490
00:57:09,349 --> 00:57:15,239
you're looking on eBay or Alibaba. What
else. We get different wafers with
491
00:57:15,239 --> 00:57:18,229
different dope agents.
And if you have something with say OK
492
00:57:18,229 --> 00:57:24,599
we're just building an n-well we have to
verify or lie on the p-base right, or on
493
00:57:24,599 --> 00:57:30,529
the p-substrate. And to avoid the obstacle
the difficulty is: we're doing twin-wells.
494
00:57:30,529 --> 00:57:36,049
We can just regulate our own dopant inside
and we are fine. We don't want to have to
495
00:57:36,049 --> 00:57:43,230
rely on the wafer or substrate itself.
What was the basic point.
496
00:57:43,230 --> 00:57:46,919
Herald: Thank you. And the last question
from microphone 2.
497
00:57:46,919 --> 00:57:52,319
Mic 2: So once you have your complete die
how about packaging and bonding because
498
00:57:52,319 --> 00:57:56,640
if you want to use it you have to place it
somehow on the PCB.
499
00:57:56,640 --> 00:58:05,140
David: Yes. So um. We have a bonding setup
at Tai Po already. That's what still is
500
00:58:05,140 --> 00:58:10,199
being used at the moment in Hong Kong is
to bond a packaging. Then we have some
501
00:58:10,199 --> 00:58:15,400
guys in HK SDP with packaging set up they
have and can make nice tape reels and they
502
00:58:15,400 --> 00:58:21,429
have also like uh after packaging tests
like: did the bonding work, is it damaged
503
00:58:21,429 --> 00:58:26,829
by the bonding, and so on. Hagen and I
have figured out some nice bonding pad
504
00:58:26,829 --> 00:58:32,819
design which didn't fit at all anymore
into the talk I already over talk like
505
00:58:32,819 --> 00:58:42,599
that. And but it absorbs the physical
stress from bonding. So we think that
506
00:58:42,599 --> 00:58:48,359
it's aluminum covered with titanium so you
don't have to sweat away any oxides right
507
00:58:48,359 --> 00:58:54,799
you have better bonding capability, better
bonding properties. So it shouldn't be
508
00:58:54,799 --> 00:58:59,309
such a problem. And we have plenty of
bonding and packaging labs which have
509
00:58:59,309 --> 00:59:04,819
already promised to help us. So it's
really like small like to choose which one
510
00:59:04,819 --> 00:59:09,890
we take.
Hagen: Just an annotation if you like a
511
00:59:09,890 --> 00:59:14,789
dedicated package please mail us. Right.
We are fixed now on the dual in-line
512
00:59:14,789 --> 00:59:21,189
package. We are thinking about flip chip
BGA but if you have other package which is
513
00:59:21,189 --> 00:59:25,829
more common for tinkerer or something like
that please mail us.
514
00:59:25,829 --> 00:59:33,970
Herald: Thank you. Thank you for the talk.
That was the talk on LibreSilicon,
515
00:59:33,970 --> 00:59:39,580
leviathan, chipforge, Andreas Westerwick
and Victor. Thank you. Thank you.
516
00:59:39,580 --> 00:59:49,549
applause
517
00:59:49,549 --> 00:59:55,179
postroll music
518
00:59:55,179 --> 01:00:12,919
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