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35c3 pre-roll music
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Herald: The next talk is the talk on[br]LibreSilicon project that's meant to
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create a free and open silicon[br]manufacturing process. And our speakers
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today are leviathan, chipforge and[br]Andreas Westerwick, creators of
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LibreSilicon. So let's give them a firm[br]round of applause and please welcome them.
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applause
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David: Oh, it works, ok. That's problem.[br]That's what essentially is all this fuss
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about is actually a description of how[br]we... what this waver means and where we
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will go with it. And yeah, I give now[br]already over to Hagen which already starts
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elaborating on the basic conceptional[br]things.
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Hagen: OK. Hello everybody. Hope you have[br]a fresh mind. It could be heavy. OK. Let's
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start. What we are. Last year David was[br]involved at the project to looking for
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free silicon, just a way to manufacture[br]his own chips and figured out it's
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difficult. You need a lot of contracts for[br]that, NDAs (non-disclosure agreements). So
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he looked around and find a clean room. We[br]had to come in and say, OK, we can rent
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it. Then he entered a scene on the last[br]Congress - a lightning talk - and said, I
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like to do that. And I wasn't in the[br]auditorium there, but a guy told me later,
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OK, look at this lightning talk. It's very[br]interesting. You'd already doing chips. So
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I entered in sees it or seen the talk[br]recording and see it. Nice idea, I will do
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that too. And the whole year we meet us by[br]mumble. It's just a thing of distance you
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know. David is located in Hong Kong. The[br]clean room is there. And I worked from
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Germany. So we exchanged e-mails. We[br]talked on a mailing list. We built up a
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small community for that and we had a[br]first hackathon just to figure it out,
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what we are doing with the tools, which[br]tools are available how we can use them,
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are they usable at all or not. And this[br]was in May and during the process the
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group wised up and already two of us got[br]their qualification to enter the clean
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room. The Hong Kong University is a[br]little bit strict in that. You have to sit
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there in the courses, you have to do exams[br]and if you're fine with the exam then you
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get the permissions to go in. So Victor[br]which is on the most left and David on
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the most right, they have the[br]qualification for that and they
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manufacture our wafer which you have seen[br]there. It's a small one, but it's the
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first stuff we have, right? OK. The basic[br]points, what we are doing. We are using
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a quite, let's see, old technologies from[br]the 80s. It's one micrometer feature size.
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It means a gate length of the transistor[br]has one micron. It's not comparable with
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all the processors you can buy now. It's[br]quite old, it's really stuff from the 80s.
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But we do it in a new way. We don't use[br]the technology from the 80s. We do it with
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the knowledge and all the experience from[br]newer technology. Doing it again and using
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some steps which are not so common, well,[br]it wasn't common in the 80s. So why one
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micron? One micron also means that the[br]transistors are very robust against five
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volt. Five volt was a usual supply voltage[br]in the 80s, 90s and something like that.
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Now the supply voltage is going down,[br]down to less than one volt but for
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tinkerers, for hobbyists, for makers, it's[br]a nice value because older stuff, many
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boards are still working with five volts[br]and we're able to handle this voltage. So
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we have a twin-well process; usually in[br]the 80s there was just one well. OK, we
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have to hurry up. We have three metal[br]layers. We have interesting additions and
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we are suitable for low tech. Ghetto tech,[br]I would say. You can use it without
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sophisticated equipment. We can analog[br]stuff and so on and analog stuff means you
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don't need small structures. OK. Areas[br]where we have to work on. First, the
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process. It's almost done. You have[br]figured out it works with measuring. OK,
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the next stuff: we need the tools. But the[br]tools are also very old and mostly not
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usable. We have to deal with that stuff.[br]We have to rethink the tooling for that
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and we need standard cells. That's my[br]task. OK, so a couple of thoughts about
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standard cells. They are very common.[br]Usually, if you have a need to translate
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your Verilog or VHDL and to bring it on a[br]silicon you need small gates. NAND gates,
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OR gates and so on. But these gates need a[br]lot of representation, the combinatorial
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sequencing. So OK. These are typical[br]cells. Just a couple of them. But imagine,
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we need much much more and there's design[br]goals for the standard cells as we need
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almost complete possibilities. If you have[br]just this small selection of cells, the
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netlist becomes huge and every gate in the[br]netlist also means a dedicated delay. If
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you have long chains we have a long delay[br]so that our operating frequency goes down.
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So if you have more complex gates we are[br]better but doing all this stuff is heavy,
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but we like to be lower power. That means[br]our cells have to be consumption less
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power than usual. We want to be fast but[br]yes, of course, it doesn't fit all
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together. OK. So we need it for[br]simulation. We need it for synthesis. We
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need it for timing. As you can see[br]everywhere on the slides and, of course,
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documentation. That's a lot of work. We[br]are a small team. I am the only guy who is
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dealing with the standard cells it's[br]usually our teams also are doing that. So
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OK, we need a tool for that which does all[br]the stuff for us. And this cell generator,
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I called it popcorn, because I put in some[br]corn and it rised up with the heat. So we
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can get all the representation. So[br]currently I have this tool on the
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repository which is Tcl which does some[br]stuff I like, I need, but not all. But it
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already seems very ugly. So for me I like[br]to rewrite that but I don't figure out
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currently which language I like to use for[br]that. Next time it could be rust, it could
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be scheme or something like that. We need[br]another language for that. So if someone
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would help - please, but that's the next[br]task, if you have the wafer done
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completely and measured. OK. That's a link[br]for the repository where you can look at
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the current status and there's a wiki[br]where I like to describe why I'm doing
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what in which way. But yes, we have to do[br]a lot more. OK.
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Andreas: OK. Hi. I take a look at the[br]current tooling that exists like
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layouting, place and route to minimize the[br]yield on the wafer. And obviously because
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this is the LibreSilicon project we look[br]at open source tools. So we have Yosys and
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graywolf, qrouter and several other FPGA[br]routers that exist. Yosys is pretty good.
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We can probably use this for the[br]synthesis. But the other tools, they lack
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very critical qualities for this... for[br]silicon because they, for example, they
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are part of qflow which is an FPGA[br]workflow. So the graywolf tool, it
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originates in academia. It's, like, it's[br]many decades old. It comes with some very
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good ideas, for example simulated[br]annealing which is a meta-heuristic
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you can use to solve NP-hard problems, but[br]it's only one of the many choices you can
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make to solve the extra hard problems. But[br]it also comes with bad implementation, for
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example inline syscalls is a very bad[br]idea. And it's also written in C and blah
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blah, OK. Qrouter is actually... it's[br]pretty good. It started in 2011 by Tim
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Edwards. It's widely used for, by hobbyists[br]and enthusiasts to route for FPGAs. But
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it's not ready for silicon and it's[br]especially not ready for our LibreSilicon
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process which would require us to to write[br]a lot of C code for Qrouter. Also
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parallelism apparently is not in scope, so[br]I mean if we want to scale up, for example
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place and route in the cloud or whatever or[br]use modern CPU architectures, we are stuck
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with sequential routing which is pretty[br]bad. Also it lacks a very important
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aspect, in my opinion, which is formal[br]correctness. So when we produce wafers in
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the fab we want to make sure that they[br]don't blow up in our faces. This is why we
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need some form of proof that our[br]algorithms are correct and therefore the
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result is correct. There are also other[br]productive tools that are proprietary
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where we can look at, but we cannot use it[br]or fork it or whatever but we can learn
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from the research that has been done, for[br]example BonnRoute. BonnRoute is used by
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IBM. The Cadence suite, I believe, is used[br]by Intel and the Alliance tools is French
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academia. Very UNIXy, I mean it's a very[br]it's a very large set of small tools that
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convert different file formats to another.[br]I mean, maybe you encountered this problem
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before when you did some hardware design;[br]you have many different file formats that
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all don't play together very well. So you[br]have tools like X to Y which convert file
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format x to y. And you see when you want[br]to place and route and layout a very very
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large chip, like a Very Large Silicon[br]Integration, then this isn't even done,
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like, automatically by tools. This is done[br]with manpower. When you look at a very
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large chip done by Intel or IBM. So this[br]is an example of a very very large chip as
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you can see. I mean do you think this has[br]been done by automation like industry 5.0?
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No. This is all manpower and a lot[br]of manpower. Which we don't have, The
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LibreSilicon project at the moment. So[br]this is the state of the art is like
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okay the manpower thing is one aspect but[br]the other thing is so what you do is
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you do placing and routing at different[br]steps at the design process so you do
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placing for a very large chip, floor[br]planning and then you do a global routing
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which is you /can imagine it like[br]routing along a rough chessboard. And
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after that you do a very detailed[br]routing where all the different
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constraints regarding your technology come[br]into play and so again the formal
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correctness aspect. So you have some[br]imperative algorithm that you cannot prove
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will blow up. And it's also not a very[br]parallel code. So you're still stuck with
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the sequential nature of the code and you[br]have no parallelism. What we propose is to
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not place and route for large chip but[br]to decompose the large chip into much
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smaller units like a component hierarchy[br]or a sub cell hierarchy and then place and
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route the small chips at the same time and[br]then reuse the small units in larger
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units. So you get an evaluation tree you[br]can work on and compile just the
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components you need. Also we propose[br]satisfiability modulo theory solvers so we
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can have some first order logic where we[br]can have constraints on the components,
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how they are placed for example they[br]don't - they must not overlap.
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Let's take the most simple example I will[br]show you like later. And also we want to
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achieve parallel or declarative code. So[br]as you can see we have some, we have many
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disagreements with academia and industry[br]which work very well together for example
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when you want to study semiconductor[br]design you have to sign some NDAs with IBM
0:16:56.420,0:17:05.699
or Intel to do that. So, they say[br]placement and routing or floor planning
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and routing are different problems and[br]they need to be solved at different times
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in the process. And then all the[br]components can be registers or NAND gates
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it does matter they all treated the same.[br]No it only matters that uh the floor
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planning stand first and then the routing[br]the closed routing then a detailed
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routing. What we propose is that place[br]and route is actually the same problem and
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that registers are different from full[br]adders. Okay. So the geographical
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partitioning of a wafer is called floor[br]planning or the placing step. And this
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results in a cut tree. So this is how they[br]do routing hierarchies. They just divide
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the wafer into smaller pieces and then do[br]the following steps based on this
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placement. What we want to do is have[br]subcell hierarchies and those sub cells
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they are either explicit like they are[br]explicitly developed for example the
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rocket ship is very modular and it has[br]many explicit verilog modules you can use
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and place and route that and then reuse[br]it. And it also has implicit sub cells like
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for example most of the time. For example[br]you have a full adder it obviously is
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composed of one bit adders so you can[br]place and route one bit adder and then
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place and route based on the one bit[br]adders that you artfully placed and routed.
0:18:56.840,0:19:00.760
And as a result you get a full adder.[br]That's just one example but I will show
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you a tree, a few slides. So there you see[br]parallelism. There's something very
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important for us. BonnRoute allocates a[br]lot of research to have some mathematical
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model for concurrency and shared memory[br]models. qrouter, which is the open source
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alternative, has none. I mean that's[br]apparently not in scope. And what I
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propose for the LibreSilicon compiler is[br]the map and reduce approach. And as I've
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mentioned you get explicit subcell[br]hierarchies through high modularization.
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That is done by the developers and[br]you also get implicit subcell hierarchies
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by compression-like algorithms that exline[br]as opposed to inline the registers or one
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bit adders. And this is also about[br]preserving these newfound hierarchies in
0:20:13.900,0:20:20.100
the compiler interfaces so you don't end[br]up inlining them again because this is
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not a Von Neumann architecture where it[br]would make sense to inline a lot of code.
0:20:24.640,0:20:30.640
So the code runs on the stack and the[br]level 1 cache. This is about reusing
0:20:30.640,0:20:42.230
components. Okay. So this is a part of the[br]rocket ship, the system bus is one
0:20:42.230,0:20:50.200
component of a very modular chip rocket[br]ship. And as you can see it is composed of
0:20:50.200,0:20:56.980
several simple lazy modules and those[br]simple modules are again composed of other
0:20:56.980,0:21:01.530
components. And then you have a lot of[br]queues and this number on the left says
0:21:01.530,0:21:08.039
how many times it's been used. For example[br]queue 15 is used 5 times in the
0:21:08.039,0:21:16.400
AXI4Deinterleaver and this is only the[br]explicit hierarchy that is declared by the
0:21:16.400,0:21:23.730
developer. Okay. Now when you apply some[br]compression-like algorithms you can
0:21:23.730,0:21:32.090
actually gain, you can get more leaves so[br]you can be even more modular. For example
0:21:32.090,0:21:39.549
queue 1 is composed of several implicit[br]modules and you can see one queue is even
0:21:39.549,0:21:46.669
reused seven times. So you just route,[br]place and route these green leaves like
0:21:46.669,0:21:51.760
once and then you can reuse it in the[br]queue 1 and everywhere where queue 1 is
0:21:51.760,0:22:02.299
reused some at some other point in the[br]chip. Now I want to state a very simple
0:22:02.299,0:22:10.270
optimization problem. What we need for[br]the process is to have components and
0:22:10.270,0:22:16.179
wires that connect the components or nets[br]and these nets and components are actually
0:22:16.179,0:22:24.200
rectilinear geometries, the components[br]shall not overlap and the nets shall
0:22:24.200,0:22:32.010
overlap with the respective pins they are[br]supposed to connect. The minimizing goals
0:22:32.010,0:22:36.470
of this optimization problem is layout[br]area, which is the most critical one
0:22:36.470,0:22:43.060
because this is what maximizes yield, the[br]maximum wire length because it's about
0:22:43.060,0:22:49.750
resistance, the wire count you want to[br]keep very small but you want to allow for
0:22:49.750,0:22:56.799
wires. The crossing number is a[br]computational thing. It doesn't really
0:22:56.799,0:23:01.460
matter for the implementation on the[br]silicon and you also want maybe you want
0:23:01.460,0:23:11.850
to minimize the wire jogs which is bends[br]in the wire. So to to solve optimization
0:23:11.850,0:23:19.309
problems in 2018 maybe you want to use an[br]abstraction from the SAT solvers. You used
0:23:19.309,0:23:25.780
to know academia came up with some pretty[br]neat theory is called satisfiability
0:23:25.780,0:23:35.220
modulo theories and you can just put some[br]first order logic and give it to a solver.
0:23:35.220,0:23:41.370
I've listed a few. For example ABC is used[br]by Yosys and Z3 from Microsoft, also very
0:23:41.370,0:23:46.780
promising product, but you can obviously[br]choose from many products by academia and
0:23:46.780,0:23:54.559
industry. Just a quick reminder what[br]boolean satisfiability is: find
0:23:54.559,0:24:00.250
assignments for all these six variables[br]which are boolean so that the whole term
0:24:00.250,0:24:06.650
is true. And now with SMT or[br]satisfiability modulo theories you can do
0:24:06.650,0:24:13.770
the same thing but now with integers and[br]also more complex data types but integers
0:24:13.770,0:24:22.950
are the most interesting. So let's do[br]something with SMT. For example we have a
0:24:22.950,0:24:29.280
component that is rectangular. And now you[br]can see this is like a Cartesian
0:24:29.280,0:24:35.260
coordinate system and you have the left[br]bottom point which is x and y and then you
0:24:35.260,0:24:41.320
have the right and the top point. And now[br]if you for example have this problem that
0:24:41.320,0:24:47.070
you don't want to have overlapping[br]rectangles you can have a rectangle A and
0:24:47.070,0:24:57.470
rectangle B and declare these coordinates[br]and then have some proposition that shall
0:24:57.470,0:25:04.290
be true and to have a proposition that[br]says they shall not overlap is to say
0:25:04.290,0:25:10.340
this. I mean it's actually the lower half[br]that makes sure that they don't overlap
0:25:10.340,0:25:15.200
and the upper half makes sure that the[br]components actually have the right
0:25:15.200,0:25:19.860
dimensions. Well in this example they[br]obviously have the same dimensions the
0:25:19.860,0:25:26.360
same components. And so you make sure[br]that the left point of the second
0:25:26.360,0:25:44.370
rectangle is right of the... Okay no,[br]never mind. One last important point I
0:25:44.370,0:25:50.370
want to make is that this this framework[br]we want to create, it's not based on the
0:25:50.370,0:25:57.760
inheritance model that we've seen in the[br]process steps right now. But we want to
0:25:57.760,0:26:02.169
combine the problems. For example the[br]overlapping problem, the pin connect
0:26:02.169,0:26:05.360
problem, and then arbitrary constraints[br]that come up during the process
0:26:05.360,0:26:10.330
development that Dave and Hagen will[br]supply me with and I will formulate that
0:26:10.330,0:26:15.390
in first order logic. And then this[br]makes sure it's formally correct and it
0:26:15.390,0:26:24.149
doesn't blow up. And as you can tell I[br]mean I've combined many NP-hard
0:26:24.149,0:26:29.480
problems at the same time but I think we[br]can manage that if we have very small
0:26:29.480,0:26:37.419
cells so I'd suggest we just stay here and[br]don't do all this for very large chips but
0:26:37.419,0:26:45.840
reuse small chips and then reuse the small[br]chips in other small chips. The silicon
0:26:45.840,0:26:54.500
compiler is one half of maximizing[br]yields. And the other half is to get the
0:26:54.500,0:27:03.260
process right so to get the process right,[br]we have David and Victor. So please.
0:27:03.260,0:27:14.030
David: So thanks for the handover. So very[br]first. There's a lot of questions why Hong
0:27:14.030,0:27:19.539
Kong. So one thing why this is a[br]really suitable place to do that is
0:27:19.539,0:27:27.490
because of history like the epic Commodore[br]64 has been made in Hong Kong. Then the
0:27:27.490,0:27:32.600
chips in the first Macintosh have been[br]made in Hong Kong and all of these
0:27:32.600,0:27:42.549
manufacturing lines. Some of them at least[br]one is still available. So also there is a
0:27:42.549,0:27:51.250
very advanced laboratory. That's the NFF,[br]Nano Fabrication Facility in
0:27:51.250,0:27:59.309
Clearwater Bay and they let us kindly use[br]their equipment to develop this process.
0:27:59.309,0:28:07.140
Also one of the sectors I mentioned[br]before, RCL semiconductors, they're really
0:28:07.140,0:28:12.270
open to introduce LibreSilicon in their[br]mass-manufacturing lines: one in Shenzen,
0:28:12.270,0:28:28.470
one in Tai Po. So in conclusion of that we[br]have advanced R&D labs there. There is
0:28:28.470,0:28:35.770
factories available. We can easily export[br]it to here over channels which already
0:28:35.770,0:28:43.840
exist. Right. And also in general it's[br]just more relaxed over there. And I don't
0:28:43.840,0:28:59.179
like minus degrees. So our process is a[br]little bit of a monster. So it makes sense
0:28:59.179,0:29:05.460
to tackle that one by one so we are right[br]now feeling ourselves upwards to get the
0:29:05.460,0:29:14.000
standard CMOS debugged, final with[br]optimized frequencies there. But we
0:29:14.000,0:29:19.210
already have on the Pearl River, I've shown[br]you, we already have test structures for
0:29:19.210,0:29:27.439
high voltage MOSFETS, B junction[br]transistors, Zener diodes, even flash,
0:29:27.439,0:29:35.010
resistors, and caps. So it's only a[br]question of effort I guess in the next few
0:29:35.010,0:29:45.620
months to get that working. When we[br]designed the process like, how it usually
0:29:45.620,0:29:50.750
works when you make a process, you look at[br]the machines you have availlable, what can
0:29:50.750,0:29:57.089
these machines do, optimum operation range[br]and then you look what substrate, what
0:29:57.089,0:30:01.220
material you have available and then you[br]start tinkering you own little proprietary
0:30:01.220,0:30:08.731
process. That's how fabs do that. And we[br]said, OK, well, to the point where we look
0:30:08.731,0:30:15.760
at the machines - what can they do? We[br]do the same, but afterwards we look that
0:30:15.760,0:30:23.950
it's portable. Not specific to the[br]equipment. So just because we have certain
0:30:23.950,0:30:29.610
machines which can do awesome things, but[br]are really exotic, doesn't mean we have to
0:30:29.610,0:30:37.690
use them. So we avoid exalting machines so[br]that it's as portable as possible. And we
0:30:37.690,0:30:43.180
also try to use wet etching whenever[br]possible in order to make sure that you
0:30:43.180,0:30:55.110
even can build it in a basement. And here[br]Evan Heisenberg may be interested now in,
0:30:55.110,0:31:02.610
you know, changing business into a less[br]dangerous business. And, yeah, they can't
0:31:02.610,0:31:06.990
be leading the innovation hub Hamburg I've[br]seen, like this improvised clean room with
0:31:06.990,0:31:15.920
just a diffusion furnace. So, that's a[br]cross-section of the... it's not
0:31:15.920,0:31:21.539
finalised, but you see a cross section[br]theoretical that's... by the way, you can
0:31:21.539,0:31:28.710
find it on GitHub as well. It's all in the[br]publications, everything we develop, all
0:31:28.710,0:31:37.830
the measurement data, all this on GitHub.[br]So that's actually the layout of these
0:31:37.830,0:31:48.260
little squares here on the wafer. You[br]see the apple in the middle. It's just in
0:31:48.260,0:31:55.929
this year. That's, uh, it's nice. I have a[br]Python script in the GDS2 generator
0:31:55.929,0:32:01.289
tool folder for Python and you[br]can take any png or anything and just
0:32:01.289,0:32:06.750
convert it into layout format, so you can[br]put your own pictures onto the metal free
0:32:06.750,0:32:14.771
layer. So in case you already have[br]interest into making little trips also.
0:32:14.771,0:32:20.570
It's also possible to make, like, ear[br]rings also with ... We don't care as long
0:32:20.570,0:32:26.580
as there are 4 more millimeters on the[br]silicon. You can put pictures on the
0:32:26.580,0:32:36.670
silicon. So that was the Pearl River[br]right. And the Pearl River fulfills the
0:32:36.670,0:32:44.620
function for us at the moment to debug all[br]the features of this LibreSilicon process.
0:32:44.620,0:32:50.651
Then the next thing we have to use it to[br]calibrate new foundries so now, we
0:32:50.651,0:32:56.250
developed it at the NFF in Clearwater Bay[br]right. And afterwards we go over to HQ
0:32:56.250,0:33:03.130
with, to the RCL guys in Tai Po, and they[br]have the machines and then we have to pipe
0:33:03.130,0:33:08.640
the Pearl River layout through there as[br]well and repeat that process over and over
0:33:08.640,0:33:15.410
again until the measurement data, like[br]the frequent, the you know the Beta
0:33:15.410,0:33:21.860
depending on Omega of the transistors and[br]the resistance of the wires and everything
0:33:21.860,0:33:28.340
kind of is the same as at NFF so that you[br]can basically, as I mentioned before one
0:33:28.340,0:33:32.870
of the design concerns is portability[br]that you can basically prototype a chip
0:33:32.870,0:33:39.860
at the NFF and then produce it in RCL or[br]in maybe some other fab in Shenzhen or
0:33:39.860,0:33:48.840
whatever. And so and if there are new[br]features coming out which also make a new
0:33:48.840,0:33:59.990
release of the Pearl River test waver and[br]we give that around they push it to GitHub
0:33:59.990,0:34:09.049
and people can introduce and calibrate the[br]process to support the new feature. And so
0:34:09.049,0:34:13.159
that's how does that work. So usually,[br]typically you have something like a photo
0:34:13.159,0:34:19.809
mask like here. I didn't bring that one[br]because it's in a clean room there and the
0:34:19.809,0:34:26.819
dust might scratch my micro structures on[br]there. So also afterwards I have to clean
0:34:26.819,0:34:31.569
it for half an hour and when I come back[br]to Hong Kong from here I'm so jetlagged I
0:34:31.569,0:34:35.492
just want to get started again, not wait[br]for the mask.
0:34:35.492,0:34:41.219
But there's a picture.[br]And these masks,
0:34:41.219,0:34:49.359
usually a stepper/aligner specific. If you[br]don't have a stepper then you need to make
0:34:49.359,0:34:56.229
a direct transfer that means you actually[br]have to put the chips in the size you
0:34:56.229,0:35:00.459
want to expose them directly onto the[br]mask. Then press the mask onto the
0:35:00.459,0:35:05.510
photoresist, expose and develop. That's[br]messy because you have to clean the mask
0:35:05.510,0:35:10.499
all the time. And it really depends. So[br]actually you can do exposure even without
0:35:10.499,0:35:15.029
a stepper. So we actually really could do[br]it also there in this university lab in
0:35:15.029,0:35:24.440
Hamburg. So all you need is a new UV[br]light. laugs So we have a little bit more
0:35:24.440,0:35:33.019
advanced tech in Hong Kong. So we have[br]here an SVG coater, this baby dispenses
0:35:33.019,0:35:40.630
automatically HPR 504, a resist. So we[br]actually just have to put in the left, you
0:35:40.630,0:35:45.589
see the cassette slot. So you put there[br]like twenty five wavers or so and then you
0:35:45.589,0:35:51.390
have a receive slot and put another[br]cassette there and it just starts sucking
0:35:51.390,0:36:01.640
in the wafers one by one, puts primer on[br]it, soft bakes it, and easy. Then you
0:36:01.640,0:36:09.859
expose it, develop it, hard bake it,[br]chilled. We have two types of resist actually
0:36:09.859,0:36:19.039
and the 6400L for the implantation[br]unfortunately has to be put in manually.
0:36:19.039,0:36:24.119
So it comes and it gives you 10 seconds[br]to open the chamber and put the resist on
0:36:24.119,0:36:31.469
it. In both cases however it doesn't[br]really matter so much because the
0:36:31.469,0:36:37.779
thickness of the resist is depending on[br]the RPMs of the spin coating unit. So you
0:36:37.779,0:36:45.269
just have to kind of put two thirds of the[br]waver should be somehow covered with the
0:36:45.269,0:36:54.190
resist and the excess resist goes away.[br]But you have to control the RPMs because
0:36:54.190,0:37:03.219
depending on when you do wet etching for[br]instance and HPR 504 has to be enough
0:37:03.219,0:37:11.059
thick because of selectivity, so that you[br]don't etch and consume the polymer,
0:37:11.059,0:37:14.760
the resist. So you have to make it thick enough[br]that you don't have,
0:37:14.760,0:37:17.590
you haven't consumed all the polymer before
0:37:17.590,0:37:23.740
you have etched your structures. And the[br]same goes for the implantation because you
0:37:23.740,0:37:41.710
need 6400L, this one can sustain higher[br]temperatures so you can use an implanter.
0:37:41.710,0:37:48.950
Now afterwards after exposure development[br]it looks like that. That's an alignment
0:37:48.950,0:37:57.079
cross for our optical stepper and for[br]instance that's our ring oscillator. So
0:37:57.079,0:38:07.020
it's one of the structures on our Pearl[br]River actually. So N well, P well. I have
0:38:07.020,0:38:11.500
to hurry up, only 10 minutes or so. So[br]that's a picture of the developing we have
0:38:11.500,0:38:16.269
some P well mask developed so we have[br]everywhere resist except in this little
0:38:16.269,0:38:22.739
crosses and stripes there. That's there[br]below is the silicon where we implant. The
0:38:22.739,0:38:32.789
recipe is easy, first coat, expose the[br]implant and then resist strip. Same for
0:38:32.789,0:38:41.480
the P well and after the resist strip you[br]can put it into a diffusion furnace in
0:38:41.480,0:38:48.809
the atmosphere for like four hours. So[br]where does the four hours come from? So
0:38:48.809,0:38:54.190
we have the Fick's equation. And the[br]Fick's equation is essentially in a
0:38:54.190,0:39:00.760
similar shape like the laplace heat[br]conduction equation, so to solve, there
0:39:00.760,0:39:07.079
are already nice solutions for it. So for[br]instance if you use boron or phosphorus
0:39:07.079,0:39:13.200
which has the nice property that they have[br]the same constants for this Dₑ. So if you
0:39:13.200,0:39:18.859
have the same temperature you basically[br]have the same Dₑ for phosphorus and boron
0:39:18.859,0:39:23.770
so you can implant them next to each[br]other and then put them at once into the
0:39:23.770,0:39:29.690
diffusion furnace and the wells are the[br]same depth. So that's why these two
0:39:29.690,0:39:36.630
materials are usually used for diffusion.[br]So that's one of the solutions that you
0:39:36.630,0:39:44.670
get, the surface for doping for the[br]threshold equation which I also will rush
0:39:44.670,0:39:53.150
through in a moment as well. The[br]equations you see here with background
0:39:53.150,0:40:02.080
doping it's a little bit much. As you have[br]here this natural logarithm inside. But
0:40:02.080,0:40:07.539
besides that you see this jump and that's[br]how you essentially build a well, you have
0:40:07.539,0:40:13.609
the background doping and you compensate[br]the donors and acceptors with each other
0:40:13.609,0:40:22.359
so that's what this absolute value of the[br]difference means. So the threshold
0:40:22.359,0:40:27.789
equation is pretty easy. And like[br]basically mirrored for PMOS and NMOS that
0:40:27.789,0:40:33.039
just like mirrored in the sense that one[br]of the transistors as PMOS is built on a N
0:40:33.039,0:40:47.069
well and NMOS is built on a P well. Right.[br]And what essentially controls the
0:40:47.069,0:40:50.930
threshold voltage, so the operational[br]voltage, which usually in the standard
0:40:50.930,0:40:59.400
CMOS is around 0.8 respectively minus[br]0.8. That's doping here like the donars
0:40:59.400,0:41:07.709
respectively acceptors and the q as[br]usually that's the oxide charge. This is
0:41:07.709,0:41:16.069
usually a process specific constant but[br]that can change. And then you get
0:41:16.069,0:41:21.709
flash, it can change Q_SS and then[br]it's flash. That's what you use in SONOS
0:41:21.709,0:41:29.469
flash, stands for silicon oxide nitride[br]oxide silicon. So there you have a
0:41:29.469,0:41:38.680
standard again, NMOS in this case but you[br]have a sandwich instead of a normal oxide
0:41:38.680,0:41:44.559
layer and for the gate oxide you have a[br]nitride and oxide. These oxide layers
0:41:44.559,0:41:53.329
above and below the nitrate are called[br]tunnel oxides. And the trick is that with
0:41:53.329,0:41:58.959
high enough energy you tunnel electrons[br]into the, through the oxide into the
0:41:58.959,0:42:04.099
nitride where it's trapped and then you[br]shift the operation voltage, the threshold
0:42:04.099,0:42:11.670
of the transistor. And when you then put[br]one at it it doesn't turn on anymore and
0:42:11.670,0:42:18.999
that's essentially how the most used flash[br]solution besides normal floating gate
0:42:18.999,0:42:27.759
works. It's really simple. So. And after[br]you get your wells out of the furnace, so
0:42:27.759,0:42:36.109
I did a little detour. You want to make[br]sure that the lateral diodes which got
0:42:36.109,0:42:41.440
into existence after diffusion don't[br]create unwanted short circuits. So we use
0:42:41.440,0:42:46.549
the technology actually developed much[br]later after one micron already has been
0:42:46.549,0:42:52.559
out. It's called STI shallow trench[br]isolation. It's from the ULSI technology
0:42:52.559,0:42:59.019
as well as the silicide we use to reduce[br]the resistance of the polysilicate.
0:42:59.019,0:43:09.319
Here are some pictures, we did etch this[br]one in the lab. That's the islands so that
0:43:09.319,0:43:14.160
around everything going down that's the[br]trenches in between the gates and between
0:43:14.160,0:43:23.500
the wells. So we isolate them from each[br]other. So the recipe is pretty easy.
0:43:23.500,0:43:26.729
So either you have a plasma[br]etcher around or if you're not
0:43:26.729,0:43:31.640
rich and don't have money to buy a plasma[br]etcher from eBay you can also get this
0:43:31.640,0:43:43.339
tetramethylammonium hydroxide. And it's[br]not even the german name, so cool, and
0:43:43.339,0:43:52.369
dilute it with deionized water 3:1 and[br]this 25% TMAH solution you heat
0:43:52.369,0:43:57.780
it up to 80°C, dip your[br]wafer in for six minutes and then you
0:43:57.780,0:44:05.440
would get your structures. Metal is[br]easier. So we did here the metal
0:44:05.440,0:44:12.309
interconnect for the ring oscillator.[br]They're etching it, also you make a
0:44:12.309,0:44:18.809
vacuum, deposit 100 nanometres aluminum,[br]30 nanometers titanium for passivation.
0:44:18.809,0:44:23.589
Take the vacuum away dip it into HF until[br]you don't see streaks on the titanium,
0:44:23.589,0:44:28.250
then into aluminum etchant until you don't[br]see streaks from the aluminum. And then
0:44:28.250,0:44:35.589
you have your wires. I'll skip[br]that one. That's just really interconnect.
0:44:35.589,0:44:44.640
But I plan to make videos soon where I go[br]through the you know like daily video blog
0:44:44.640,0:44:49.539
of results but just that you see that you[br]see the oxide depending on the angle it
0:44:49.539,0:44:57.630
has different colors. So that's L2 the[br]isolation. And then you see the
0:44:57.630,0:45:04.019
topological measurement device. You see[br]this one micron because we only deposited
0:45:04.019,0:45:12.709
a micron for now. You'll see the heights[br]the differences and we see that one micron
0:45:12.709,0:45:17.719
is not enough. So we'd still have these[br]sharp edges which we don't want. So we have
0:45:17.719,0:45:23.959
back in Hong Kong have to deposit another[br]2 microns. And if you want a follow up you
0:45:23.959,0:45:31.479
go to my Github. OK? So Victor that's him[br]and I have done that so far. It's only
0:45:31.479,0:45:36.699
like two weeks because it took a lot of[br]time to get all the masks manufactured and
0:45:36.699,0:45:41.789
so a lot of bureaucracy. We already have[br]that much and just stay tuned. We already
0:45:41.789,0:45:46.819
have figured out so much in the last two[br]weeks that it shouldn't be long before we
0:45:46.819,0:45:57.779
can well finish all the features of Pearl[br]River. Create models with Hawkins popcorn
0:45:57.779,0:46:02.640
and start figuring out all the analog[br]stuff for our MCU and then we make
0:46:02.640,0:46:07.219
an MCU. That's the first thing we want to[br]do as soon as we have the features figured
0:46:07.219,0:46:17.409
out of Pearl River. If the Goddess is nice[br]to us. Yeah it's a discordia figurine,
0:46:17.409,0:46:23.319
it's really cheap on ebay. laugs[br]So yeah. And that's like an overall
0:46:23.319,0:46:30.700
of the features. And we want them build[br]this microcontroller, and yes because all
0:46:30.700,0:46:34.279
the folks don't believe that there are[br]people who want to buy such items you
0:46:34.279,0:46:45.319
please fill out the survey. That one[br]is from Hagens trip, i skipped it but
0:46:45.319,0:46:50.380
yeah. So yeah. Thanks. I'm done. And too[br]late but sorry.
0:46:50.380,0:47:00.900
applause
0:47:00.900,0:47:05.770
Herald: Thank you for the talk. No, but if[br]you wait we have time for questions. So
0:47:05.770,0:47:10.770
there are two microphones. One is in the[br]middle and one is on the left side of the
0:47:10.770,0:47:16.410
stage. Line up and we're going to take[br]some questions and there is already one
0:47:16.410,0:47:23.269
question from Microphone number two.[br]Microphone 2: OK. So thank you for that
0:47:23.269,0:47:28.700
interesting talk and all the development[br]that you're doing. I was wondering have
0:47:28.700,0:47:37.900
you had any time to test your transistors[br]yet. And then later on do you plan to
0:47:37.900,0:47:42.852
release some sort of analog simulation[br]capabilities.
0:47:42.852,0:47:48.709
David: Yes. Thats the plan for the next[br]few weeks after I'm back in Hongkong. We
0:47:48.709,0:47:53.329
did go back to the cleanroom. We actually[br]wanted to provide already something for the
0:47:53.329,0:48:00.669
Congress. Unfortunately we were noticed,[br]short noticed that Thursday and Friday
0:48:00.669,0:48:06.289
they take the wet stations and the[br]machines offline for maintenance of the
0:48:06.289,0:48:13.140
AC. So we have already like, the wafer, we[br]have the isolation oxides but we didn't
0:48:13.140,0:48:19.119
have any time left to actually test the[br]the you know only having polysilicon is
0:48:19.119,0:48:22.730
not enough. You have to also have metal to[br]go with probes there, that stuff is
0:48:22.730,0:48:27.279
micron size.[br]Hagen: Okay. So your question as I
0:48:27.279,0:48:31.730
understand was in the direction of[br]simulation right? We like to measure all
0:48:31.730,0:48:38.279
the structures we have to produce and with[br]the values we get we like to feed in spice
0:48:38.279,0:48:45.789
models. So you can do analog simulations.[br]And yes we like to use this technology for
0:48:45.789,0:48:50.369
analog stuff because as I already[br]mentioned one micron size is enough for
0:48:50.369,0:48:56.279
analog. You don't need smaller structures.[br]Analog all this having huge transistor
0:48:56.279,0:49:03.849
size from 20 or 50 Microns. So they[br]are huge, you don't need this small
0:49:03.849,0:49:11.349
technology. So they are quite feasible for[br]analog stuff but let's say in this way if
0:49:11.349,0:49:16.150
you're doing analog stuff in a[br]conventional way you have to sign all the
0:49:16.150,0:49:21.259
NDAs and you're stuck on this technology[br]you're using. You can't transfer your
0:49:21.259,0:49:27.170
design to the next fab because in the next[br]fab the PDKs are different. You have to
0:49:27.170,0:49:31.380
transfer or to translate all the[br]structures there for a rebuild again for
0:49:31.380,0:49:36.250
the new technology if you have a[br]technology which you can take from one fab
0:49:36.250,0:49:42.720
to another like our one. You are quite[br]happy because the analog stuff you
0:49:42.720,0:49:49.400
designed once also fits for the next fab.[br]So yes of course we like to support analog
0:49:49.400,0:49:54.529
stuff. We need help for that of course we[br]have to measure, we are currently
0:49:54.529,0:49:58.150
developing the wafer, we are currently[br]working on the documents how to measure,
0:49:58.150,0:50:02.799
what we like to measure and then we have[br]to transfer the values to spice. But we
0:50:02.799,0:50:08.799
have documented how we are doing that.[br]And so everyone can use the knowledge.
0:50:08.799,0:50:12.209
Mic 2: Thank you.[br]Herald: Thank you. Mike one please.
0:50:12.209,0:50:17.069
Mic 1: Do you have any plans for [br]open source mask production like.
0:50:17.069,0:50:25.920
David: Yes. Actually the problem is only[br]that as I mentioned before. If you want to
0:50:25.920,0:50:30.390
have an opto mask for steppers that's[br]always manufacturer specific. If you want
0:50:30.390,0:50:37.529
to have a direct transfer mask not a[br]problem. So I guess so Sam is really
0:50:37.529,0:50:44.680
helpful in the lab. He runs the laser[br]scriber. We could talk with the folks at
0:50:44.680,0:50:51.499
NFF. They were really lovely helpful[br]really. They really like to really help us
0:50:51.499,0:50:58.959
a lot. And now that we talk with RCL.[br]They also have laser scribers that we could
0:50:58.959,0:51:04.660
actually also start producing masks in the[br]long run. So yes that's certainly one of
0:51:04.660,0:51:13.150
the things I intend to do is providing[br]optical masks for exposure. Um yeah.
0:51:13.150,0:51:17.180
Herald: Thank you. Uh one more question[br]from microphone two.
0:51:17.180,0:51:25.009
Mic 2: Great talk thanks. I'm really[br]interested in the - what it would take to
0:51:25.009,0:51:31.039
build the fab. What's the minimum set[br]of tools. We've already seen a couple of
0:51:31.039,0:51:37.559
orders of cost reduction in, through DIY[br]bio hacking by making the tooling a lot
0:51:37.559,0:51:44.299
cheaper. Do you see that happening within[br]the nearest decades and your sort of work?
0:51:44.299,0:51:51.250
David: Yes. So for instance I made my[br]process by purpose this way that you can
0:51:51.250,0:51:56.640
actually improvise most of it like the LTL[br]growing and deposition and everything with
0:51:56.640,0:52:02.390
a furnace. So what you need is a wet[br]etcher like some wet etch station. You can
0:52:02.390,0:52:08.200
actually there is a video from Jeri[br]Ellsworth called "making microchips
0:52:08.200,0:52:16.210
at home cooking with Jeri" and he does[br]microchips in the kitchen so it's
0:52:16.210,0:52:21.489
not, you get scared like HFS, it dissolves[br]your bones and so on and then you see the
0:52:21.489,0:52:25.390
guys who already have qualified, are[br]qualified or employed there: they just
0:52:25.390,0:52:33.739
without any PPE, nothing just grab into[br]the HF. That's just the skill to scare
0:52:33.739,0:52:40.509
folks from generating insurance problems.[br]In general it's not really that dangerous
0:52:40.509,0:52:48.069
right. You can do the stuff at home. No[br]problem. Yeah. So we intend. So this
0:52:48.069,0:52:55.999
process I made is so trivial. So we have[br]also a branch called super low tech. We
0:52:55.999,0:53:02.039
just shall essentially but it's more RnD.[br]But you could actually help there for
0:53:02.039,0:53:08.150
instance figure out the last details,[br]get a furnace from eBay put it onto your
0:53:08.150,0:53:17.410
kitchen table start RnD-ing make some git[br]pull requests and we're super happy. Okay.
0:53:17.410,0:53:22.109
So it's doable and the furnace you get on[br]ebay. So no problem.
0:53:22.109,0:53:29.559
Herald: Thank you. Microphone 1 again.[br]Mic 1: So you just said about the
0:53:29.559,0:53:33.660
analog stuff that a lot of that is usually[br]under NDA from the fab. So have you
0:53:33.660,0:53:38.509
encountered any problems with the fab and[br]that you're currently using in that you're
0:53:38.509,0:53:43.789
actually trying to discover these[br]processes for yourself like you're
0:53:43.789,0:53:48.089
generating competition that they might not[br]like, have you had any problems with that.
0:53:48.089,0:53:54.939
David: Oh no I had a nice phone calls,[br]e-mails with the owner of the fab over in
0:53:54.939,0:54:01.960
Tai Po who also has a second branch in[br]Shenzhen that's RCL. I actually asked him
0:54:01.960,0:54:08.109
recently "Hey is it okay when I use your[br]logo in the presentation and implicitly
0:54:08.109,0:54:13.319
make an advertisement for your fab here?"[br]No prob go ahead. That is like...
0:54:13.319,0:54:18.579
He's really eager to, LibreSilicon[br]is what they need because every fab
0:54:18.579,0:54:24.269
usually has to invest money in to develop[br]it. First they develop a proprietary
0:54:24.269,0:54:30.069
process right, or they license some[br]proprietary process from another company
0:54:30.069,0:54:38.260
and then they have to invest RnD costs to[br]develop IP cores for their setup. With
0:54:38.260,0:54:43.920
LibreSilicon the problem is solved for[br]the companies because these foundry is
0:54:43.920,0:54:49.099
using LibreSilicon everything the[br]community develops is on github. And
0:54:49.099,0:54:55.689
that's the IP catalog essentially.[br]So they don't have to invest any
0:54:55.689,0:55:00.380
additional money into RnD-ing IP cores[br]that's in the nature of open source that
0:55:00.380,0:55:05.799
there are IP cores popping into existence[br]all the time. They can focus on the thing
0:55:05.799,0:55:10.940
they're best at: making silicon, right? So[br]it's actually positive but only for the
0:55:10.940,0:55:15.579
small foundries that are really interested[br]especially Shenzhen and now some in India
0:55:15.579,0:55:22.420
and some of the big foundries and they[br]will not, they are anyway the big
0:55:22.420,0:55:27.089
companies have the tendency to be as[br]mobile as a cargo ship. So it will take at
0:55:27.089,0:55:32.069
least like two years until they[br]acknowledge that LibreSilicon exists and
0:55:32.069,0:55:39.869
then we might expect some legal you know[br]bullying. But for now they won't even they
0:55:39.869,0:55:46.390
just laugh right. They just laugh at best.
0:55:46.390,0:55:49.819
Herald: We're going to have two more[br]questions before we're out of time.
0:55:49.819,0:55:54.459
Microphone 2.[br]Mic 2: Why did you go for the twin well
0:55:54.459,0:55:57.650
process as opposed to the simpler single[br]well?
0:55:57.650,0:56:02.180
David: Uhm that's a good point. That's[br]also something with portability and if you
0:56:02.180,0:56:06.769
have different events or different[br]supplier for substrate it might be that in
0:56:06.769,0:56:13.559
n-doped or un-doped substrate. So with[br]twin well architecture and actually we
0:56:13.559,0:56:18.360
have on the n-well we also built p-bases[br]and in these n-bases, so we have actually
0:56:18.360,0:56:27.519
like stacked wells in the n-wells and[br]p-wells. So actually it's a one two. Um
0:56:27.519,0:56:35.969
Pentagon Well I don't know. Um and it's[br]just that you can shift to
0:56:35.969,0:56:42.819
the doping of the n- and the p-substrate.[br]According that you fit LibreSilicon
0:56:42.819,0:56:48.259
requirements to still have the physical[br]properties ensured by LibreSilicon. No
0:56:48.259,0:56:53.009
matter whether you get your substrate from[br]somewhere from Great Britain or from
0:56:53.009,0:57:01.160
TaoBao.[br]Hagen: Okay. The thing is we looked before
0:57:01.160,0:57:09.349
at eBay which wafer we can get. Currently[br]NFF is supporting us with wafers. But if
0:57:09.349,0:57:15.239
you're looking on eBay or Alibaba. What[br]else. We get different wafers with
0:57:15.239,0:57:18.229
different dope agents.[br]And if you have something with say OK
0:57:18.229,0:57:24.599
we're just building an n-well we have to[br]verify or lie on the p-base right, or on
0:57:24.599,0:57:30.529
the p-substrate. And to avoid the obstacle[br]the difficulty is: we're doing twin-wells.
0:57:30.529,0:57:36.049
We can just regulate our own dopant inside[br]and we are fine. We don't want to have to
0:57:36.049,0:57:43.230
rely on the wafer or substrate itself.[br]What was the basic point.
0:57:43.230,0:57:46.919
Herald: Thank you. And the last question[br]from microphone 2.
0:57:46.919,0:57:52.319
Mic 2: So once you have your complete die[br]how about packaging and bonding because
0:57:52.319,0:57:56.640
if you want to use it you have to place it[br]somehow on the PCB.
0:57:56.640,0:58:05.140
David: Yes. So um. We have a bonding setup[br]at Tai Po already. That's what still is
0:58:05.140,0:58:10.199
being used at the moment in Hong Kong is[br]to bond a packaging. Then we have some
0:58:10.199,0:58:15.400
guys in HK SDP with packaging set up they[br]have and can make nice tape reels and they
0:58:15.400,0:58:21.429
have also like uh after packaging tests[br]like: did the bonding work, is it damaged
0:58:21.429,0:58:26.829
by the bonding, and so on. Hagen and I[br]have figured out some nice bonding pad
0:58:26.829,0:58:32.819
design which didn't fit at all anymore[br]into the talk I already over talk like
0:58:32.819,0:58:42.599
that. And but it absorbs the physical[br]stress from bonding. So we think that
0:58:42.599,0:58:48.359
it's aluminum covered with titanium so you[br]don't have to sweat away any oxides right
0:58:48.359,0:58:54.799
you have better bonding capability, better[br]bonding properties. So it shouldn't be
0:58:54.799,0:58:59.309
such a problem. And we have plenty of[br]bonding and packaging labs which have
0:58:59.309,0:59:04.819
already promised to help us. So it's[br]really like small like to choose which one
0:59:04.819,0:59:09.890
we take.[br]Hagen: Just an annotation if you like a
0:59:09.890,0:59:14.789
dedicated package please mail us. Right.[br]We are fixed now on the dual in-line
0:59:14.789,0:59:21.189
package. We are thinking about flip chip[br]BGA but if you have other package which is
0:59:21.189,0:59:25.829
more common for tinkerer or something like[br]that please mail us.
0:59:25.829,0:59:33.970
Herald: Thank you. Thank you for the talk.[br]That was the talk on LibreSilicon,
0:59:33.970,0:59:39.580
leviathan, chipforge, Andreas Westerwick[br]and Victor. Thank you. Thank you.
0:59:39.580,0:59:49.549
applause
0:59:49.549,0:59:55.179
postroll music
0:59:55.179,1:00:12.919
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