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36c3 preroll music
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Herald: Our next talk will be "The[br]ultimate Acorn Archimedes Talk", in which
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there will be spoken about everything[br]about the Archimedes computer. There's a
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promise in advance that there will be no[br]heureka jokes in there. Give a warm
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welcome to Matt Evans.
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applause
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Matt Evans: Thank you. Okay. Little bit of[br]retro computing first thing in the
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morning, sort of. Welcome. My name is Matt[br]Evans. The Acorn Archimedes was my
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favorite computer when I was a small[br]hacker and I'm privileged to be able to
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talk a bit little bit about it with you[br]today. Let's start with: What is an Acorn
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Archimedes? So I'd like an interactive[br]session, I'm afraid. Please indulge me,
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like a show of hands. Who's heard of the[br]Acorn Archimedes before? Ah, OK, maybe 50,
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60%. Who has used one? Maybe 10%,[br]maybe. Okay. Who has programs -
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who has coded on an Archimedes? Maybe[br]half? Two, three people. Great. Okay.
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Three. laughs Okay, so a small[br]percentage. I don't see these machines as
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being as famous as say the Apple Macintosh[br]or IBM PC. And certainly outside of Europe
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they were not that common. So this is kind[br]of interesting just how many people here
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have seen this. So it was the first ARM-[br]based computer. This is an astonishingly
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1980s - I think one of them is drawing,[br]actually. But they're not just the first
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ARM-based machine, but the machine that[br]the ARM was originally designed to drive.
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It's a... Is that a comment for me?[br]Mic?
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I'm being heckled already. It's only slide[br]two. Let's see how this goes. So it's a
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two box computer. It looks a bit like a[br]Mega S.T. ... to me. Its main unit with
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the processor and disks and expansion[br]cards and so on. Now this is an A3000.
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This is mine, in fact, and I didn't bother[br]to clean it before taking the photo. And
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now it's on this huge screen. That was a[br]really bad idea. You can see all the
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disgusting muck in the keyboard. It has a[br]bit of ink on it, I don't know why. But
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this machine is 30 years old. And[br]this was luckily my machine, as I said, as
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a small hacker. And this is why I'm doing[br]the talk today. This had a big influence
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on me. I'd like to say as a person, but[br]more as an engineer. In terms of what my
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programing experience when I was learning[br]to program and so on. So I live and work
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in Cambridge in the U.K., where this[br]machine was designed. And through the
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funny sort of turn of events, I ended up[br]there and actually work in the building
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next to the building where this was[br]designed. And a bunch of the people that
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were on that original team that designed[br]this system are still around and
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relatively contactable. And I thought this[br]is a good opportunity to get on the phone
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and call them up or go for a beer with a[br]couple of them and ask them: Why are
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things the way they are? There's all sorts[br]of weird quirks to this machine. I was
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always wondering this, for 20 years. Can[br]you please tell me - why did you do it
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this way? And they were a really good bunch[br]of people. So I talked to Steve Ferber,
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who led the hardware design, Sophie[br]Wilson, who was the same with software.
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Tudor Brown, who did the video system.[br]Mike Miller, the IO system. John Biggs and
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Jamie Urquhart , who did the silicon[br]design, I spoiled one of the
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surprises here. There's been some silicon[br]design that's gone on in building this
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Acorn. And they were all wonderful people[br]that gave me their time and told me a
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bunch of anecdotes that I will pass on to[br]you. So I'm going to talk about the
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classic Arc. There's a bunch of different[br]machines that Acorn built into the 1990s.
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But the ones I'm talking about started in[br]1987. There were 2 models, effectively a
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low end and a high end. One had an option[br]for a hard disk, 20 megabytes, 2300
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pounds, up to 4MB of RAM. They all share[br]the same basic architecture, they're all
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basically the same. So the A3000 that I[br]just showed you came out in 1989. That was
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the machine I had. Those again, the same.[br]It had the memory controller slightly
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updated, was slightly faster. They all had[br]an ARM 2. This was the released version of
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the ARM processor designed for this[br]machine, at 8 MHz. And then finally in
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1990, what I call the last of the classic[br]Arc, Archimedes, is the A540. This was the
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top end machine - could have up to[br]16 MB of memory, which is a fair bit
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even in 1990. It had a 30 MHz ARM 3. The[br]ARM 3 was the evolution of the ARM 2, but
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with a cache and a lot faster. So this[br]talk will be centered around how these
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machines work, not the more modern[br]machines. So around 1987, what else
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was available? This is a random selection[br]of machines. Apologies if your favorite
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machine is not on this list. It wouldn't[br]fit on the slide otherwise. So at the
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start of the 80s, we had the exotic things[br]like the Apple Lisa and the Apple Mac.
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Very expensive machines. The Amiga - I had[br]to put in here. Started off relatively
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expensive because the Amiga 500 was, you[br]know, very good value for money, very
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capable machine. But I'm comparing this[br]more to PCs and Macs, because that was the
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sort of, you know, market it was going[br]for. And although it was an expensive
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machine compared to Macintosh, it was[br]pretty cheap. Even put NeXT Cube on there,
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I figured that... I'd heard that they were[br]incredibly expensive. And actually
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compared to the Macintosh, they're not[br]that expensive at all. Well I don't know
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which one I would have preferred. So the[br]first question I asked them - the first
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thing they told me: Why was it built? I've[br]used them in school and as I said, had one
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at home. But I was never really quite sure[br]what it was for. And I think a lot of the
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Acorn marketing wasn't quite sure what it[br]was for either. They told me it was the
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successor to the BBC Micro, this 8 bit[br]machine. Lovely 6502 machine, incredibly
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popular, especially in the UK. And the[br]goal was to make a machine that was 10
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times the performance of this. The[br]successor would be 10 times faster at the
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same price. And the thing I didn't know is[br]they had been inspired. The team Acorn had
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seen the Apple Lisa and the Xerox Star,[br]which comes from the famous Xerox Alto,
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Xerox PARC, first GUI workstation in the[br]70s, monumental machine. They'd been
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inspired by these machines and they wanted[br]to make something very similar. So this is
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the same story as the Macintosh. They[br]wanted to make something that was desktop
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machine for business, for office[br]automation, desktop publishing and that
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kind of thing. But I never really[br]understood this before. So this was this
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inspiration came from the Xerox machines.[br]It was supposed to be obviously a lot more
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affordable and a lot faster. So this is[br]what happens when Acorn marketing gets
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hold of this vision. So Xerox Star on the[br]left is this nice, sensible business
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machine. Someone's wearing nice, crisp[br]suit bumps microphon banging their
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microphone - and it gets turned into the[br]very Cambridge Tweed version on the right.
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It's apparently illegal to program one of[br]these if you're not wearing a top hat. But
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no one told me that when I was a kid. And[br]my court case comes up next week. So
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Cambridge is a bit of a funny place. And[br]for those that been there, this picture on
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the right sums it all up. So they began[br]Project A, which was build this new
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machine. And they looked at the[br]alternatives. They looked at the
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processors that were available at that[br]time, the 286, the 68 K, then that semi
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32016, which was an early 32 bit[br]machine, a bit of a weird processor. And
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they all had something in common that[br]they're ridiculously expensive and in
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Tudors words a bit crap. They weren't a[br]lot faster than the BBC Micro. They're a
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lot more expensive. They're much more[br]complicated in terms of the processor
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itself. But also the system around them[br]was very complicated. They need lots of
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weird support chips. This just drove the[br]price up of the system and it wasn't going
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to hit that 10 times performance, let[br]alone at the same price point. They'd
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visited a couple of other companies[br]designing their own custom silicon. They
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got this idea in about 1983. They were[br]looking at some of the RISC papers coming
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out of Berkeley and they were quite[br]impressed by what a bunch of grad students
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were doing. They managed to get a working[br]RISC processor and they went to Western
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Design Center and looked at 6502[br]successors being design there. They had a
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positive experience. They saw a bunch of[br]high school kids with Apple 2s doing
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silicon layout. And they though "OK,[br]well". They'd never designed a CPU before
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at ACORN. ACORN hadn't done any custom[br]silicon to this degree, but they were
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buoyed by this and they thought, okay,[br]well, maybe RISC is the secret and we can
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do this. And this was not really the done[br]thing in this timeframe and not for a
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company the size of ACORN, but they[br]designed their computer from scratch. They
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designed all of the major pieces of[br]silicon in this machine. And it wasn't
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about designing the ARM chip. Hey, we've[br]got a processor core. What should we do
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with it? But it was about designing the[br]machine that ARM and the history of that
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company has kind of benefited from. But[br]this is all about designing the machine as
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a whole. They're a tiny team. They're a[br]handful of people - about a dozen...ish
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that did the hardware design, a similar[br]sort of order for software and operating
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systems on top, which is orders of[br]magnitude different from IBM and Motorola
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and so forth that were designing computers[br]at this time. RISC was the key. They
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needed to be incredibly simple. One of the[br]other experiences they had was they went
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to a CISC processor design center. They[br]had a team in a couple of hundred people
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and they were on revision H and it still[br]had bugs and it was just this unwieldy,
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complex machine. So RISC was the secret.[br]Steve Ferber has an interview somewhere.
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He jokes about ACORN management giving him[br]two things. Special sauce was two things
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that no one else had: He'd no people and[br]no money. So it had to be incredibly
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simple. It had to be built on a[br]shoestring, as Jamie said to me. So there
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are lots of corners cut, but in the right[br]way. I would say "corners cut", that
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sounds ungenerous. There's some very[br]shrewd design decisions, always weighing
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up cost versus benefit. And I think they[br]erred on the correct side for all of them.
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So Steve sent me this picture. That's he's[br]got a cameo here. That's the outline of
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him in the reflection on the glass there.[br]He's got this up in his office. So he
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led the hardware design of all of these[br]chips at ACORN. Across the top, we've got
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the original ARM, the ARM 1, ARM 2 and the[br]ARM 3 - guess the naming scheme - and the
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video controller, memory controller and IO[br]controller. Think, sort of see their
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relative sizes and it's kind of pretty.[br]This was also on a processor where you
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could really point at that and say, "oh,[br]that's the register file and you can see
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the cache over there". You can't really do[br]that nowadays with modern processors. So
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the bit about the specification, what it[br]could do, the end product. So I mentioned
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they all had this ARM 2 8MHz, up to four[br]MB of RAM, 26-bit addresses, remember
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that. That's weird. So a lot of 32-bit[br]machines, had 32-bit addresses or the ones
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that we know today do. That wasn't the[br]case here. And I'll explain why in a
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minute. The A540 had a updated CPU. The[br]memory controller had an MMU, which was
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unusual for machines of the mid 80s. So it[br]could support, the hardware would support
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virtual memory, page faults and so on. It[br]had decent sound, it had 8-channel sound,
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hardware mixed and stereo. It was 8 bit,[br]but it was logarithmic - so it was a bit
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like u-law, if anyone knows that - instead[br]of PCM, so you got more precision at the
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low end and it sounded to me a little bit[br]like 12 bit PCM sound. So this is quite
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good. Storage wise, it's the same floppy[br]controller as the Atari S.T.. It's fairly
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boring. Hard disk controller was a[br]horrible standard called ST506, MFM
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drives, which were very, very crude[br]compared to disks we have today. Keyboard
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and mouse, nothing to write home about. I[br]mean, it was a normal keyboard. It was
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nothing special going on there. And[br]printer port, serial port and some
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expansion slots which, I'll[br]outline later on. The thing I really liked
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about the ARC was the graphics[br]capabilities. It's fairly capable,
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especially for a machine of that era and[br]of the price. It just had a flat frame
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buffer so it didn't have sprites, which is[br]unfortunate. It didn't have a blitter and
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a bitplanes and so forth. But the upshot[br]of that is dead simple to program. It had
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a 256 color mode, 8 bits per pixel, so[br]it's a byte, and it's all just laid out as
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a linear string of bytes. So it was dead[br]easy to just write some really nice
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optimized code to just blit stuff to the[br]screen. Part of the reason why there isn't
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a blitter is actually the CPU was so good[br]at doing this. Colorwise, it's got
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paletted modes out of a 4096 color[br]palette, same as the Amiga. It has this
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256 color mode, which is different. The[br]big high end machines, the top end
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machines, the A540 and the A400 series[br]could also do this very high res 1152 by
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900, which was more of a workstation[br]resolution. If you bought a Sun
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workstation a Sun 3 in those days, could[br]do this and some higher resolutions. But
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this is really not seen on computers that[br]might have in the office or school or
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education at the end of the market. And[br]it's quite clever the way they did that.
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I'll come back to that in a sec. But for[br]me, the thing about the ARC: For the
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money, it was the fastest machine around.[br]It was definitely faster than 386s and all
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the stuff that Motorola was doing at the[br]time by quite a long way. It is almost
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eight times faster than a 68k at about the[br]same clock speed. And it's to do with it's
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pipelineing and to do with it having a 32[br]bit word and a couple of other tricks
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again. I'll show you later on what the[br]secret to that performance was. About
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minicomputer speed and compared to some of[br]the other RISC machines at the time, it
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wasn't the first RISC in the world, it was[br]the first cheap RISC and the first RISC
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machine that people could feasibly buy and[br]have on their desks at work or in
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education. And if you compare it to[br]something like the MIPS or the SPARC, it
0:14:19.222,0:14:25.300
was not as fast as a MIPS or SPARC chip.[br]It was also a lot smaller, a lot cheaper.
0:14:25.300,0:14:29.240
Both of those other processers had very[br]big Die. They needed other support chips.
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They had huge packages, lots of pins, lots[br]of cooling requirements. So all this
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really added up. So I priced up[br]a Sun 4 workstation at the time and
0:14:36.180,0:14:40.050
it was well over four times the price of[br]one of these machines. And that was before
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you add on extras such as disks and[br]network interfaces and things like that.
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So it's very good, very competitive for[br]the money. And if you think about building
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a cluster, then you could get a lot more[br]throughput, you could network them
0:14:50.140,0:14:56.980
together. So this is about as far as I got[br]when I was a youngster, I was wasn't brave
0:14:56.980,0:15:03.230
enough to really take the machine apart[br]and poke around. Fortunately, now it's 30
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years old and I'm fine. I'm qualified and[br]doing this. I'm going to take it apart.
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Here's the motherboard. Quite a nice clean[br]design. This was built in Wales for anyone
0:15:12.089,0:15:17.510
that's been to the UK. Very unusual these[br]days. Anything to be built in the UK. It's
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got several main sections around these[br]four chips. Remember the Steve photo
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earlier on? This is the chip set: the ARM[br]BMC, PDC, IOC. So the IOC side of things
0:15:29.470,0:15:34.090
happens over on the left video and sound[br]in the top right. And the memory and the
0:15:34.090,0:15:38.399
processor in the middle. It's got a[br]megabyte onboard and you can plug in an
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expansion for 4 MB. So memory map[br]from the software view. I mentioned this
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26-bit addressing and I think this is one[br]of the key characteristics of one of these
0:15:46.930,0:15:52.210
machines. So you have a 64MB address[br]space, it's quite packed. That's quite a
0:15:52.210,0:15:56.980
lot of stuff shoehorned into here. So[br]there's the memory. The bottom half of the
0:15:56.980,0:16:02.040
address space, 32MB of that is the[br]processor. It's got user space and
0:16:02.040,0:16:08.100
privilege mode. It's got a concept of[br]privilege within the processor execution.
0:16:08.100,0:16:11.851
So when you're in user mode, you only get[br]to see the bottom half and that's the
0:16:11.851,0:16:16.250
virtual maps. There's the MMU, that will[br]map pages into that space and then when
0:16:16.250,0:16:18.980
you're in supervisor mode, you get to see[br]the whole of the rest of the memory,
0:16:18.980,0:16:23.380
including the physical memory and various[br]registers up the top. The thing to notice
0:16:23.380,0:16:27.460
here is: there's stuff hidden behind the[br]ROM, this address space is very packed
0:16:27.460,0:16:31.390
together. So there's a requirement[br]for control registers, for the memory
0:16:31.390,0:16:34.770
controller, for the video controller and[br]so on, and they write only registers in
0:16:34.770,0:16:39.700
ROM basically. So you write to the ROM and[br]you get to hit these registers. Kind of
0:16:39.700,0:16:43.730
weird when you first see it, but it was[br]quite a clever way to fit this stuff into
0:16:43.730,0:16:50.810
the address space. So it will start with[br]the ARM1. So Sophie Wilson designed the
0:16:50.810,0:16:59.070
instruction set late 1983, Steve took the[br]instruction set and designed the top
0:16:59.070,0:17:02.880
level, the block, the micro architecture[br]of this processor. So this is the data
0:17:02.880,0:17:08.140
path and how the control logic works. And[br]then the VLSI team, then implemented this,
0:17:08.140,0:17:12.420
did their own custom cells. There's a[br]custom data path and custom logic
0:17:12.420,0:17:18.179
throughout this. It took them about a[br]year, all in. Well, 1984, that sort of...
0:17:18.179,0:17:23.832
This project A really kicked off early[br]1984. And this staked out first thing
0:17:23.832,0:17:34.690
early 1985. The design process the guys[br]gave me a little bit of... So Jamie
0:17:34.690,0:17:40.800
Urquhart and John Biggs gave me a bit of[br]an insight into how they worked on the
0:17:40.800,0:17:46.870
VLSI side of things. So they had an Apollo[br]workstation, just one Apollo workstation,
0:17:46.870,0:17:51.760
the DN600. This is a 68K based washing[br]machine, as Jamie described it. It's this
0:17:51.760,0:17:56.180
huge thing. It cost about 50˙000 £.[br]It's incredibly expensive. And they
0:17:56.180,0:18:00.220
designed all of this with just one of[br]these workstations. Jamie got in at 5:00
0:18:00.220,0:18:04.060
a.m., worked until the afternoon and then[br]let someone else on the machine. So they
0:18:04.060,0:18:06.760
shared the workstation, they worked[br]shifts so that they could design this
0:18:06.760,0:18:10.020
whole thing on one workstation. So this[br]comes back to that. It was designed on a
0:18:10.020,0:18:13.660
bit of a shoestring budget. When they got[br]a couple of other workstations later on in
0:18:13.660,0:18:17.760
the projects, there was an allegation that[br]the software might not have been licensed
0:18:17.760,0:18:21.950
initially on the other workstations and[br]the CAD software might have been. I can
0:18:21.950,0:18:28.450
neither confirm nor deny whether that's[br]true. So Steve wrote a BBC Basic
0:18:28.450,0:18:33.300
simulator for this. When he's designing[br]this block level micro architecture run on
0:18:33.300,0:18:38.750
his BBC Micro. So this could then run real[br]software. There could be a certain amount
0:18:38.750,0:18:41.570
of software development, but then they[br]could also validate that the design was
0:18:41.570,0:18:46.820
correct. There's no cache on this. This is[br]a quite a large chip. 50 square
0:18:46.820,0:18:52.290
millimeters was the economic limit of[br]those days for this part of the market.
0:18:52.290,0:18:56.100
There's no cache. That also would have[br]been far too complicated. So this was
0:18:56.100,0:19:03.120
also, I think, quite a big risk, no pun[br]intended. The aim of doing this
0:19:03.120,0:19:07.620
with such a small team that they're all[br]very clever people. But they hadn't all
0:19:07.620,0:19:11.490
got experience in building chips before.[br]And I think they knew what they were up
0:19:11.490,0:19:15.100
against. And so not having a cache of[br]complicated things like that was the right
0:19:15.100,0:19:20.910
choice to make. I'll show you later that[br]that didn't actually affect things. So
0:19:20.910,0:19:24.810
this was a RISC machine. If anyone has not[br]programmed ARM in this room then get out
0:19:24.810,0:19:29.400
at once. But if you have programed ARM[br]this is quite familiar with some
0:19:29.400,0:19:36.210
differences. It's a classical three[br]operand RISC, its got three shift on one of
0:19:36.210,0:19:38.790
the operands for most of the instructions.[br]So you can do things like static
0:19:38.790,0:19:43.820
multiplies quite easily. It's not purist[br]RISC though. It does have load or store
0:19:43.820,0:19:47.980
multiple instructions. So these will, as[br]the name implies, load or store multiple
0:19:47.980,0:19:51.460
number of registers in one go. So one[br]register per cycle, but it's all done
0:19:51.460,0:19:54.970
through one instruction. This is not RISC.[br]Again, there's a good reason for doing
0:19:54.970,0:19:59.300
that. So when one comes back and it gets[br]plugged into a board that looks a bit like
0:19:59.300,0:20:07.400
this. This is called the A2P, the ARM second[br]processor. It plugs into a BBC Micro. It's
0:20:07.400,0:20:11.280
basically there's a thing called the Tube,[br]which is sort of a FIFO like arrangement.
0:20:11.280,0:20:15.230
The BBC Micro can send messages one way[br]and this can send messages back. And the
0:20:15.230,0:20:20.250
BBC Micro has the discs, it has the I/O,[br]keyboard and so on. And that's used as the
0:20:20.250,0:20:23.960
hosts to then download code into one[br]megabytes of RAM up here and then you
0:20:23.960,0:20:29.010
combine the code on the ARM. So this was[br]the initial system, 6 MHz. The
0:20:29.010,0:20:32.350
thing I found quite interesting about[br]this, I mentioned that Steve had built
0:20:32.350,0:20:37.200
this BBC Basic simulation, one of the[br]early bits of software that could run on
0:20:37.200,0:20:41.870
this. So he'd ported BBC Basic to ARM and[br]written an ARM version of it. The Basic
0:20:41.870,0:20:47.780
interpreter was very fast, very lean, and[br]it was running on this board early on.
0:20:47.780,0:20:51.750
They then built a simulator called ASIM,[br]which was an event based simulator for
0:20:51.750,0:20:55.240
doing logic design and all of the other[br]chips in the chips on the chipset that
0:20:55.240,0:20:59.020
were simulated using ASIM on ARM1 which is[br]quite nice. So this was the fastest
0:20:59.020,0:21:02.480
machine that they had around. They didn't[br]have, you know, the thousands of machines
0:21:02.480,0:21:07.730
in the cluster like you'd have in a[br]modern company doing EDA. They had
0:21:07.730,0:21:11.370
a very small number of machines and these[br]were the fastest ones they had about. So
0:21:11.370,0:21:17.450
ARM2 was simulated on ARM1 and all the[br]other chipset. So then ARM2 comes along.
0:21:17.450,0:21:21.590
So it's a year later, this is a shrink of[br]the design. It's based on the same basic
0:21:21.590,0:21:26.000
micro architecture but has a multiplier[br]now. It's a booth multiplier , so it is at
0:21:26.000,0:21:32.090
worst case, 16 cycle, multiply just two[br]bits per clock. Again, no cache. But one
0:21:32.090,0:21:36.950
thing they did add in on to is banked[br]registers. Some of the processor modes I
0:21:36.950,0:21:42.940
mentioned there's an interrupt mode. Next[br]slide, some of the processor modes will
0:21:42.940,0:21:47.960
basically give you different view on[br]registers, which is very useful. These
0:21:47.960,0:21:51.090
were all validated at 8 MHz. So[br]the product was designed for 8 MHz.
0:21:51.090,0:21:54.020
The company that built them[br]said, okay, put the stamp on the outside
0:21:54.020,0:21:57.681
saying 8 MHz. There's two[br]versions of this chip and I think they're
0:21:57.681,0:22:01.390
actually the same silicon. I've got a[br]suspicion that they're the same. They just
0:22:01.390,0:22:05.420
tested this batch saying that works at 10[br]or 12. So on my project list is
0:22:05.420,0:22:12.270
overclocking my A3000 to see how fast[br]it'll go and see if I can get it to 12 MHz.
0:22:12.270,0:22:18.559
Okay. So the banking of the registers.[br]ARM has got this even modern 32 bit
0:22:18.559,0:22:25.060
type of interrupts and an IRQ[br]pronounced "erk" in English and FIQ
0:22:25.060,0:22:28.559
pronounced "fic" in English. I appreciate it[br]doesn't mean quite the same thing in
0:22:28.559,0:22:34.290
German. So I call if FIQ from here on in[br]and FIQ mode has this property where
0:22:34.290,0:22:37.830
the top half of the registers are effectively[br]different registers when you get into
0:22:37.830,0:22:42.670
this mode. So this lets you first of all[br]you don't have to back up those registers.
0:22:42.670,0:22:47.950
I mean your FIQ handler. And[br]secondly if you can write an FIQ handler
0:22:47.950,0:22:51.970
using just those registers and there's[br]enough for doing most basic tasks, you
0:22:51.970,0:22:55.940
don't have to save and restore anything[br]when you get an interrupt. So this is
0:22:55.940,0:23:02.510
designed specifically to be very, very low[br]overhead interrupt mode. So I'm coming to
0:23:02.510,0:23:07.890
why there's a 26 bit address space. And so[br]I found this link very unintuitive. So
0:23:07.890,0:23:13.520
unlike 32 bit ARM, the more modern[br]1990s onwards ARMs, the program counter
0:23:13.520,0:23:17.020
register 15 doesn't just contain the[br]program counter, but also contains the
0:23:17.020,0:23:20.420
status flags and processor mode and[br]effectively all of the machine state is
0:23:20.420,0:23:24.200
packed in there as well. So I asked the[br]question, well why, why 64 megabytes of
0:23:24.200,0:23:27.700
address space? What's special about 64.[br]And Mike told me, well, you're asking the
0:23:27.700,0:23:31.980
wrong question. It's the other way round.[br]What we wanted was this property that all
0:23:31.980,0:23:35.990
of the machine state is in one register.[br]So this means you just have to save one
0:23:35.990,0:23:40.000
register. Well, you know, what's the harm[br]in saving two registers? And he reminded
0:23:40.000,0:23:43.490
me of this FIQ mode. Well, if you're[br]already in a state where you've really
0:23:43.490,0:23:47.890
optimized your interrupt handler so that[br]you don't need any other registers to deal
0:23:47.890,0:23:51.390
with, you're not saving restoring anything[br]apart from your PC, then saving another
0:23:51.390,0:23:56.000
register is 50 percent overhead on that[br]operation. So that was the prime motivator
0:23:56.000,0:24:00.500
was to keep all of the state in one word.[br]And then once you take all of the flags
0:24:00.500,0:24:04.600
away, you're left with 24 bits for a word[br]aligned program counter, which leads to
0:24:04.600,0:24:09.799
26 bit addressing. And that was then seen[br]as well, 64 MB is enough. There were
0:24:09.799,0:24:14.690
machines in 1985 that, you know, could[br]conceivably have more memory than that.
0:24:14.690,0:24:18.260
But for a desktop that was still seen as a[br]very large, very expensive amount of
0:24:18.260,0:24:24.450
memory. The other thing, you don't need to[br]reinvent another instruction to do
0:24:24.450,0:24:28.170
return from exception so you can return[br]using one of your existing instructions.
0:24:28.170,0:24:32.740
In this case, it's the subtract into PC[br]which looks a bit strange, but trust me,
0:24:32.740,0:24:39.030
that does the right thing. So the memory[br]controller. This is - I mentioned the
0:24:39.030,0:24:43.040
address translation, so this has an MMU in[br]it. In fact, the thing directly on the
0:24:43.040,0:24:46.080
left hand side. I was[br]worried that these slides actually might
0:24:46.080,0:24:49.520
not be the right resolution and they might[br]be sort of too small for people to see
0:24:49.520,0:24:53.570
this. And in fact, it's the size of a[br]house is really useful here. So the left
0:24:53.570,0:24:58.500
hand side of this chip is the MMU. This[br]chip is the same size as ARM 2. Yeah,
0:24:58.500,0:25:02.380
pretty much. So that's part of the reason[br]why the MMU is on another chip ARM2 was
0:25:02.380,0:25:06.610
as big as they could make it to fit the[br]price as you don't have anyone here done
0:25:06.610,0:25:10.810
silicon design. But as the the area goes[br]up effectively your yield goes down and
0:25:10.810,0:25:14.690
the price it's it's a non-linear effect on[br]price. So the MMU had to be on a separate
0:25:14.690,0:25:19.910
chip and it's half the size of that as[br]well. MEMC does most mundane things
0:25:19.910,0:25:23.920
like it drives DRAM, it does refresh for[br]DRAM and it converts from linear addresses
0:25:23.920,0:25:33.799
into row and column addresses which DRAM[br]takes. So the key thing about this
0:25:33.799,0:25:39.090
ARM and MEMC binding is the key factor of[br]performance is making use of memory
0:25:39.090,0:25:43.740
bandwidth. When the team had looked at all[br]the other processors in Project A before
0:25:43.740,0:25:49.380
designing their own, one of the things[br]they looked at was how well they utilized
0:25:49.380,0:25:56.320
DRAM and 68K and the semi chips made very,[br]very poor use of DRAM bandwidth.
0:25:56.320,0:25:59.940
Steve said, well, okay. The DRAM is the[br]most expensive component of any of these
0:25:59.940,0:26:04.280
machines and they're making poor use of[br]it. And I think a key insight here is if
0:26:04.280,0:26:07.740
you maximize that use of the DRAM, then[br]you're going to be able to get much higher
0:26:07.740,0:26:13.490
performance in those machines. And so it's[br]32 bits wide. The ARM is pipelined, so it can
0:26:13.490,0:26:18.730
do a 32 bit word every cycle. And it also[br]indicates whether it's sequential or non
0:26:18.730,0:26:25.250
sequential addressing. This[br]then lets your MEMC
0:26:25.250,0:26:31.200
decide whether to do an N cycle or an S[br]cycle. So there's a fast one and a slow
0:26:31.200,0:26:35.220
one basically. So when you access a new[br]random address and DRAM, you have to open
0:26:35.220,0:26:40.710
that row and that takes twice the time.[br]It's a 4 MHz cycle. But then once
0:26:40.710,0:26:45.150
you've access that address and then once[br]you're accessing linearly ahead of that
0:26:45.150,0:26:49.599
address, you can do fast page mode[br]accesses, which are 8 MHz cycles.
0:26:49.599,0:26:54.030
So ultimately, that's the reason[br]why these load store multiples exist. The
0:26:54.030,0:26:57.820
non-RISC instructions, they're there so[br]that you can stream out registers and back
0:26:57.820,0:27:03.100
in and make use of this DRAM bandwidth. So[br]store multiple. This is just a simple
0:27:03.100,0:27:07.860
calculation for 14 registers, you're[br]hitting about 25 megabytes a second out of
0:27:07.860,0:27:13.083
30. So this is it's not 100%, but it's way[br]more than a 10th or an 8th.
0:27:13.083,0:27:16.880
Which a lot of the other processors[br]were using. So this was really good. This
0:27:16.880,0:27:21.170
is the prime factor of why this machine[br]was so fast. It's effectively the load store
0:27:21.170,0:27:28.069
multiple instructions and being able to[br]access the stuff linearly. So the MMU is
0:27:28.069,0:27:36.980
weird. It's not TLB in the traditional[br]sense, so TLB's today, if you take your
0:27:36.980,0:27:43.040
MIPS chip or something where the TLB is[br]visible to software, it will map a virtual
0:27:43.040,0:27:47.760
address into a chosen physical address and[br]you'll have some number of entries and you
0:27:47.760,0:27:53.880
more or less arbitrarily, you know, poke[br]an entry and with the set mapping in it.
0:27:53.880,0:27:57.789
The MEMC does it upside down. So it says it's[br]got a fixed number of entries for every
0:27:57.789,0:28:02.380
page in DRAM. And then for each of those[br]entries, it checks an incoming address to
0:28:02.380,0:28:08.600
see whether it matches. So it has all of[br]those entries that we've showed on the
0:28:08.600,0:28:13.500
chip diagram a couple of slides ago. That[br]big left hand side had that big array. All
0:28:13.500,0:28:16.831
of those effectively just storing a[br]virtual address and then matching it and
0:28:16.831,0:28:20.030
have a comparator. And then one of them[br]lights up and says yes, it's mine. So
0:28:20.030,0:28:24.551
effectively, the aphysical page says that[br]virtual address is mine instead of the
0:28:24.551,0:28:30.030
other way round. So this also limits your[br]memory. If you're saying I have to have
0:28:30.030,0:28:34.480
one of these entries on chip per page of[br]physical memory and you don't want pages
0:28:34.480,0:28:40.720
to be enormous. The 32 K if you do the[br]maths is 4 MB over 128 pages, it's a
0:28:40.720,0:28:44.460
32K page. If you don't want the page to[br]get much bigger than that and trust me you
0:28:44.460,0:28:47.890
don't, then you need to add more of these[br]entries and it's already half the size of
0:28:47.890,0:28:52.540
the chip. So effectively, this is one of[br]the limits of why you can only have 4 MB
0:28:52.540,0:28:58.360
on one of these memory[br]controller chips. OK. So VIDC is the core
0:28:58.360,0:29:05.230
of the video and sound system. It's set a[br]FIFO is and a set of shift digital analog
0:29:05.230,0:29:09.970
converters for doing video and sound[br]stream stuff into the FIFO zone. It does
0:29:09.970,0:29:14.850
the display timing and pallet lookup and[br]so forth. It has an 8 bit mode I
0:29:14.850,0:29:21.840
mentioned. It's slightly strange. It also[br]has an output for transparency bit. So in
0:29:21.840,0:29:23.830
your palette you can sense 12 bits of[br]color, but you can set a bit of
0:29:23.830,0:29:31.910
transparency as well so you can do video[br](gen?) looking quite easily with this. So
0:29:31.910,0:29:36.701
there was a revision later on Tudor[br]explains that the very first one had a bit
0:29:36.701,0:29:41.230
of crosstalk between the video and the[br]sound, so you'd get sound with noise on
0:29:41.230,0:29:45.980
it. That was basically video noise and[br]it's quite hard to get rid of. And so they
0:29:45.980,0:29:50.000
did this revision and the way he fixed it[br]was quite cool. They shuffled the power
0:29:50.000,0:29:54.000
supply around and did all the sensible[br]engineering things. But he also filtered
0:29:54.000,0:29:58.610
out a bit of the noise that is being[br]output on the that's the sound. He
0:29:58.610,0:30:02.630
inverted it and then fed that back in as[br]the reference current for the DAC. So that
0:30:02.630,0:30:06.090
sort of self compensating and took the[br]noise a bit like the noise canceling
0:30:06.090,0:30:10.809
headphones. So it was kind of a nice hack.[br]And that was that was VIDC1. OK, the final
0:30:10.809,0:30:17.700
one, I'm going to stop showing you chip[br]plots after this, unfortunately, but just
0:30:17.700,0:30:20.980
get your fill while we're here. And again,[br]I'm really glad this is enormous for the
0:30:20.980,0:30:25.590
people in the room and maybe those zooming[br]in online. There's a cool little
0:30:25.590,0:30:29.510
Illuminati eye logo in the bottom left[br]corner. So I feared that you weren't gonna
0:30:29.510,0:30:34.630
be able to see and I didn't have time to[br]do zoomed in version, but. Okay. So I see
0:30:34.630,0:30:38.030
is the center of the IOC system as much of[br]the IO system as possible? All the random
0:30:38.030,0:30:41.030
bits of blue logic to do things like[br]timing. Some peripherals are slower than
0:30:41.030,0:30:47.309
others lives in IOC. It contains a UART[br]for the keyboard, so the keyboard is
0:30:47.309,0:30:52.320
looked after by an 851 microcontroller.[br]Just nice and easy to do. Scanning in
0:30:52.320,0:30:57.429
software. This microcontroller just sends[br]stuff up of serial port to this chip. So
0:30:57.429,0:31:02.039
UART keyboard, asynchronous receiver and[br]transmitter. It was at one point called
0:31:02.039,0:31:06.080
the fast asynchronous receiver and[br]transmitter. Mike got forced to change the
0:31:06.080,0:31:12.730
name. Not everyone has a 12 year old sense[br]of humor, but I admire his spirit. So the
0:31:12.730,0:31:15.630
other thing it does is interrupts all the[br]interrupts go into IOC and it's got masks
0:31:15.630,0:31:20.341
and consolidates them effectively for[br]sending an interrupt up to the on the ARM
0:31:20.341,0:31:24.690
can then check the status to a fast[br]response to it. So the eye of providence
0:31:24.690,0:31:27.540
there, the little logo I pointed out, Mike[br]said you put that in for future
0:31:27.540,0:31:35.799
archaeologists to wonder about.Okay That[br]was that was it. I was hoping there'd be
0:31:35.799,0:31:40.500
this big back story about, you know, he[br]was in the Illuminati or something. Maybe
0:31:40.500,0:31:44.690
he is not allowed to say anyway. So just[br]like the other Dave Porter showed, you say
0:31:44.690,0:31:49.930
this one's A 500 to B, it's still a second[br]processor that plugs into a BBC Micro.
0:31:49.930,0:31:54.460
It's still got this this hosts having disk[br]drives and so forth attached to it and
0:31:54.460,0:32:00.289
pushing stuff down the tube into the[br]memory here. But now, finally, all of the
0:32:00.289,0:32:05.370
all of this, the chips that are now[br]assembled in one place. So this is
0:32:05.370,0:32:08.370
starting to look like an Archimedes. It[br]got video out. It's got keyboard
0:32:08.370,0:32:11.620
interface. It's got some expansion stuff.[br]So this is bring up an early software
0:32:11.620,0:32:18.460
headstart. But very shortly afterwards, we[br]got the a five A500 internal 2 Acorn. And
0:32:18.460,0:32:21.460
this is really the first Archimedes. This[br]is the prototype. Archimedes actually got
0:32:21.460,0:32:27.660
a gorgeous gray brick sort of look to it,[br]kind of concrete. It weighs like concrete,
0:32:27.660,0:32:31.480
too, but it has all the hallmarks. It's[br]got the. IO interfaces, it's got the
0:32:31.480,0:32:36.950
expansion slots. It can see at the back.[br]It's got all it runs the same operating
0:32:36.950,0:32:39.950
system. Now, this was used for the OS[br]development. There's only a couple of
0:32:39.950,0:32:44.820
hundred of these made. Well, this is a[br]serial 2 2 2. So this is one of the last,
0:32:44.820,0:32:50.730
I think. But yeah. Only an internal to[br]ACORN. There is a nice tweaks to this
0:32:50.730,0:32:55.700
machine. So the hardware team had designed[br]this Tudor design this as well as the
0:32:55.700,0:33:01.710
video system. And he said, well, his A500[br]was the special one that he had a video
0:33:01.710,0:33:05.409
control of the heat. He'd hand-picked one[br]of the videos so that instead of running
0:33:05.409,0:33:11.190
at 24 megahertz to 56, so some silicon[br]variations in manufacturer. So he found a
0:33:11.190,0:33:16.169
56 megahertz pipe. And so he could do. I[br]think it was 1024 x 768, which is way out
0:33:16.169,0:33:22.400
of respect for the rest of the Archimedes.[br]So he had the really, really cool machine.
0:33:22.400,0:33:26.220
They also ran some of them at 12 megahertz[br]as well instead of 8. This is a massive
0:33:26.220,0:33:30.500
performance improvement. I think it use[br]expensive memory, which is kind of out of
0:33:30.500,0:33:37.180
reach for the product. Right. So believe[br]me, this is the simplified circle, the
0:33:37.180,0:33:41.240
circuit diagram. The technical reference[br]manuals are available online if anyone
0:33:41.240,0:33:46.159
wants the complicated one. The main parts[br]of the display are ARM , MEMC and some RAM
0:33:46.159,0:33:52.049
and we have a little walk through them. So[br]the clocks are generated actually by the
0:33:52.049,0:33:57.200
memory controller. Memory controller gives[br]the clocks the ARM. The main reason for
0:33:57.200,0:34:01.030
this is that the memory controller has to[br]do some slow things now and then. It has
0:34:01.030,0:34:05.860
to open pages of DRAMs, refresh cycles and[br]things. So it stops the CPU and generates
0:34:05.860,0:34:11.559
the clock and it pauses the CPU by[br]stopping that clock from time to time.
0:34:11.559,0:34:16.079
When you do a DRAM access, your adress on[br]bus along the top, the arm outputs an
0:34:16.079,0:34:19.720
address that goes into the memory. The[br]MEMCthen converts that, it does an address
0:34:19.720,0:34:23.599
translation and then it converts that into[br]a row and column addresses sheet with
0:34:23.599,0:34:27.139
them. And then if you're doing a reading[br]and outputs the address aehm outputs the
0:34:27.139,0:34:33.419
data onto the date bus, which on then sees[br]this kind of menses, the critical path on
0:34:33.419,0:34:37.279
this. But the address flows through memory[br]effectively. Notice that MEMC is not on
0:34:37.279,0:34:41.329
the data bus. It just gets addresses[br]flowing through it become important later
0:34:41.329,0:34:47.260
on ROM is another slow things. Another[br]reason why memory might slow down the
0:34:47.260,0:34:54.099
access and in a similar sort of way. There[br]is also a permission check done when
0:34:54.099,0:35:00.259
you're doing the address translation per[br]user permission versus I was a supervisor
0:35:00.259,0:35:06.640
and so this information's output as part[br]of the cycle when when he does access. If
0:35:06.640,0:35:09.730
you miss and that translation, you get a[br]page false or permission fault, then an
0:35:09.730,0:35:17.410
abort signal comes back and you take an[br]exception on deals with that in software.
0:35:17.410,0:35:22.289
The database is a critical path, and so[br]the IO stuff is buffered, it is kept away
0:35:22.289,0:35:27.599
from that. So the IO bus is 16 bits and[br]not a lot 32 bit peripherals around in
0:35:27.599,0:35:32.599
those days that will the peripherals 8 or[br]16 bits. So that's the right thing to do.
0:35:32.599,0:35:36.150
The IOC decodes that and there's a[br]handshake with memory if it needs more
0:35:36.150,0:35:39.809
time, if it's accessing one of the[br]expansion cards in the expansion card. Is
0:35:39.809,0:35:47.691
that something slow on X then that's dealt[br]with in the IOC. So I mentioned the
0:35:47.691,0:35:53.680
interrupt status that gets funneled into[br]IOC and then back out again. There's a V
0:35:53.680,0:35:57.599
Sync interrupt, but not an H Sync[br]interrupt. You have to use timers for that
0:35:57.599,0:36:02.010
really annoyingly. There's one timer and[br]there's a 2 megahertz timer available. I
0:36:02.010,0:36:05.539
think I had in a previous life not[br]previously mentioned it. So if you want to
0:36:05.539,0:36:09.730
do funny palette switching stuff or copper[br]bars or something as possible with the
0:36:09.730,0:36:13.400
timers, it's also simple hardware mod to[br]make a real HD sync interrupt as well.
0:36:13.400,0:36:18.529
There's some spare interrupt inputs on the[br]IOC as an exercise for you . So the bit I
0:36:18.529,0:36:23.440
really like about this system, I mentioned[br]that MEMC is not on the data bus. The VIDC
0:36:23.440,0:36:28.079
is only on the data bus and it doesn't[br]have an address by C. Then the VIDC is the
0:36:28.079,0:36:31.200
thing responsible for turning the frame[br]buffer into video reading that frame
0:36:31.200,0:36:35.509
buffer out of RAM, so on. So how does it[br]actually do that? DRam read without the
0:36:35.509,0:36:40.960
address? Well, the memory contains all of[br]the registers for doing this DNA. The
0:36:40.960,0:36:45.140
start of the frame buffer, the current[br]position and size and so on. They will
0:36:45.140,0:36:51.410
live in the MEMC. So there's a handshake[br]where VIDC sends a request up to the MEMC.
0:36:51.410,0:36:55.239
When it's FIFO gets low, the memory then[br]actually generates the address into the
0:36:55.239,0:37:00.349
DRAM diagram, DRAM outputs that data and[br]then gives the memory, gives an
0:37:00.349,0:37:05.509
acknowledged to the... I mean...too many[br]chips. The memory gives an acknowledged to
0:37:05.509,0:37:11.210
VIDC, which then matches that data into[br]the into the FIFO. So this partitioning is
0:37:11.210,0:37:16.710
quite neat. A lot of the video, DMA, while[br]the video DMA all lives in MEMC and
0:37:16.710,0:37:20.799
there's this kind of split across the two[br]chips. The sound one I've just
0:37:20.799,0:37:24.839
highlighted, one interrupt that comes from[br]MEMC. Sound works exactly the same way,
0:37:24.839,0:37:27.730
except there's a double buffering scheme[br]that goes on. And when one half of it
0:37:27.730,0:37:32.359
becomes empty, you get an interrupt so you[br]can be sure that so you don't get your
0:37:32.359,0:37:39.700
sound. So this this all works really very[br]smoothly. So finally the high res mono
0:37:39.700,0:37:44.509
thing that I mentioned before is quite[br]novel way they did that to do had realized
0:37:44.509,0:37:49.931
that with one external component to the[br]shift register and running very fast, he
0:37:49.931,0:37:53.400
could implement this very high resolution[br]mode without really affecting the rest of
0:37:53.400,0:38:00.099
the chip. So VIDC still runs at 24[br]megahertz to sort of PGA resolution. The
0:38:00.099,0:38:05.450
outputs on a digital bus that was a test[br]boardoriginally. It outputs 4 bits. So 4
0:38:05.450,0:38:09.420
pixels in one chunk at 24 megahertz and[br]then this external component then shifts
0:38:09.420,0:38:13.880
through that 4 times the speed. There's[br]one component. I mean, this is this is a
0:38:13.880,0:38:17.569
very cheap way of doing this. And as I[br]said, this this high res mode is very
0:38:17.569,0:38:23.009
unusual for machines of this of this era.[br]I've got a feeling and a 500 the top end
0:38:23.009,0:38:26.979
machine, if anyone's got one of these and[br]wants to try this trick and please get in
0:38:26.979,0:38:31.080
touch, I've got a feeling and a five[br]hundred will do 1280 x 1024 by
0:38:31.080,0:38:35.750
overclocking this. I think all of the[br]parts survive it. But for some reason,
0:38:35.750,0:38:40.369
ACORN didn't support that on the board.[br]And finally, clock selection obviously on
0:38:40.369,0:38:44.839
some of the machines, quite flexible set[br]of clocks for different resolutions,
0:38:44.839,0:38:51.589
basically. So MEMC is not on the data bus.[br]How do we program it? It's got registers
0:38:51.589,0:38:55.259
for DNA and it's got all this address[br]translation. So the memory map I showed
0:38:55.259,0:39:01.089
before has an 8 megabyte space reserve for[br]the address translation registers doesn't
0:39:01.089,0:39:04.690
have eight megabytes of it. I mean,[br]doesn't have two million 32 bit registers
0:39:04.690,0:39:09.819
behind them, which is a hint of what's[br]going on here. So what you do is you write
0:39:09.819,0:39:14.410
any value to this space and you encode the[br]information that you want to put into one
0:39:14.410,0:39:19.539
of these registers in the address. So this[br]address, the top three bits, the one it's
0:39:19.539,0:39:25.230
in the top eight megabytes of the 64[br]megabyte address space and you format your
0:39:25.230,0:39:28.999
logical physical page information in this[br]address and then you write any byte
0:39:28.999,0:39:35.479
effectively. This is a sort of feels[br]really dirty, but also really a very nice
0:39:35.479,0:39:39.779
way of doing it because there's no other[br]space in the address map. And this reads
0:39:39.779,0:39:45.069
to the the price balance. So it's not[br]worth having an address bus going into
0:39:45.069,0:39:49.809
MEMC costing 32 more pins just to write[br]these registers as opposed to playing this
0:39:49.809,0:39:55.849
sort of trick. If you have that address.[br]But adjust for that database just for
0:39:55.849,0:39:59.990
that, then you know, you have to get to a[br]more expensive package. And this was this
0:39:59.990,0:40:05.140
was really in their minds a 68 pin chip[br]versus an 84 pin chip. It was a big deal,
0:40:05.140,0:40:08.719
right. So everything they really strived[br]to make sure it was in the very smallest
0:40:08.719,0:40:13.250
package possible. And this system[br]partitioning effort led to these sorts of
0:40:13.250,0:40:22.890
tricks to then then program it. So on the[br]A540, we get multiple MEMCs. Each one is
0:40:22.890,0:40:27.329
assigned a colored stripe here of the[br]physical address space. So you have a 16
0:40:27.329,0:40:31.049
megabyte space, each one looks after four[br]megabytes of it. But then when you do a
0:40:31.049,0:40:36.039
virtual access in the bottom half of the[br]user space, regular program access, all of
0:40:36.039,0:40:40.080
them light up and all of them will[br]translate that address in parallel. And
0:40:40.080,0:40:44.290
one of them hopefully will translate and[br]then energize the RAM to do the read. For
0:40:44.290,0:40:49.930
example, when you put an ARM 3 in this[br]system, on three has its cache and then
0:40:49.930,0:40:54.420
the address leads into the memory. So then[br]that means that the address is being
0:40:54.420,0:40:58.240
translated outside of the cache or after[br]the cache. So your caching virtual
0:40:58.240,0:41:02.900
addresses and as we all know, this is kind[br]of bad for performance because whenever
0:41:02.900,0:41:06.749
you change that virtual address space, you[br]have to invalidate your cache target. But
0:41:06.749,0:41:11.799
they didn't do that. There's other ways of[br]solving this problem. Basically on this
0:41:11.799,0:41:14.950
machine, what you need to do is invalidate[br]the whole cache. It's quite a quick
0:41:14.950,0:41:24.150
operation, but it's still not good for[br]performance to have an empty cache. The
0:41:24.150,0:41:28.730
only DMA present in the system is for the[br]video, for the video and sound. I/O
0:41:28.730,0:41:32.569
doesn't have any DMA at all. And this is[br]another area where as younger engineers
0:41:32.569,0:41:35.969
see crap, why didn't they have DMA? That[br]would be way better. DMA is the solution
0:41:35.969,0:41:40.989
to everyone's problems, as we all know.[br]And I think the quote on the right hand
0:41:40.989,0:41:47.390
ties in with the ACORN team's discovery[br]that all of these other processes needed
0:41:47.390,0:41:51.969
quite complex chipsets, quite expensive[br]support chips. So the quote on the right
0:41:51.969,0:41:56.539
says that if you've got some chips, that[br]vendors will be charging more for their
0:41:56.539,0:42:03.259
DMA devices even than the CPU. So not[br]having dedicated DMA engine on board is a
0:42:03.259,0:42:08.930
massive cost saving. The comment I made on[br]the previous to slide about the system
0:42:08.930,0:42:14.440
partitioning, putting a lot of attention[br]into how many pins were on one chip versus
0:42:14.440,0:42:19.380
another, how many buses were going around[br]the place. Not having IOC having to access
0:42:19.380,0:42:25.019
memory was a massive saving and cost for[br]the number of pins and the system as a
0:42:25.019,0:42:33.539
whole. The other thing is the the FIQ mode[br]was effectively the means for doing IO.
0:42:33.539,0:42:37.999
Therefore, FIQ Mode was designed to be an[br]incredibly low overhead way of doing
0:42:37.999,0:42:44.010
programed IO by having the CPU, you do the[br]IO. So this was saying that the CPU is
0:42:44.010,0:42:48.850
going to be doing all of the IO stuff, but[br]lets just optimize it, let's make it make
0:42:48.850,0:42:53.930
it as good as it could be and that's what[br]led to the threatened IO (?). I also
0:42:53.930,0:42:57.849
remember ARM 2 didn't have a cache. If you[br]don't have a cache on your CPU you can.
0:42:57.849,0:43:03.099
DMA is going to hold up the CPU anyway, so[br]we'll know cycles. DMA is not any
0:43:03.099,0:43:06.960
performance. Again, you may as well get[br]the CPU to do it and then get the CPU to
0:43:06.960,0:43:13.029
do it in the lowest overhead way possible.[br]I think this can be summarized as bringing
0:43:13.029,0:43:17.410
the "RISC principles" to the system. So[br]the RISC principle, say for your CPU, you
0:43:17.410,0:43:21.420
don't put anything in the CPU that you can[br]do in software and this is saying, okay,
0:43:21.420,0:43:26.789
we'll actually software can do the IO just[br]as well without the cache as the DMA
0:43:26.789,0:43:29.799
system. So let's get software to do that.[br]And I think this is a kind of a nice way
0:43:29.799,0:43:34.339
of seeing it. This is part of the cost[br]optimization for really very little
0:43:34.339,0:43:39.910
degradation in performance compared to[br]doing in hardware. So this is an IO card.
0:43:39.910,0:43:43.380
The euro cards then nice and easy. The[br]only thing I wanted to say here was this
0:43:43.380,0:43:49.339
is my SCSI card and it has a ROM on the[br]left hand side. And so. This is the
0:43:49.339,0:43:54.339
expansion ROM basically many, many years[br]before PCI made this popular. Your drivers
0:43:54.339,0:43:58.950
are on this ROM. This is a SCSI disc[br]plugging into this and you can plug this
0:43:58.950,0:44:02.990
card in and then boot off the desk. You[br]don't need any other software to make it
0:44:02.990,0:44:07.670
work. So this is just a very nice user[br]experience. There is no messing around
0:44:07.670,0:44:11.690
with configuring IO windows or interrupts[br]or any of the ISIS sort of stuff that was
0:44:11.690,0:44:17.869
going on at the time. So to summarize some[br]of the the hardware stuff that we've seen,
0:44:17.869,0:44:21.950
the AMAs pipeline and it has the load-[br]store-multiple -instructions which make
0:44:21.950,0:44:27.950
for a very high bandwidth utilization.[br]That's what gives it its high performance.
0:44:27.950,0:44:32.670
The machine was really simple. So[br]attention to detail about separating,
0:44:32.670,0:44:37.239
partitioning the work between the chips[br]and reducing the chip cost as much as
0:44:37.239,0:44:44.569
possible. Keeping that balanced was really[br]a good idea. The machine was designed when
0:44:44.569,0:44:49.400
memory and CPUs were about the same speed.[br]So this is before that kind of flipped
0:44:49.400,0:44:52.910
over. An eight megahertz on two is[br]designed to use 8 megahertz memory.
0:44:52.910,0:44:56.509
There's no need to have a cache at all on[br]there these days. It sounds really crazy
0:44:56.509,0:45:01.410
not to have a cache on you, but if your[br]memory is not that much slower than this
0:45:01.410,0:45:07.809
is a huge cost saving, but it is also risk[br]saving This was the first real proper CPU.
0:45:07.809,0:45:11.670
If we don't count ARM 1 to say oh, was a[br]test, but ARM 2 is that, you know, the
0:45:11.670,0:45:16.490
first product, CPU. And having a cache on[br]that would have been a huge risk for a
0:45:16.490,0:45:20.640
design team that hadn't hadn't dealt with[br]structures that complicated it at that
0:45:20.640,0:45:26.299
point. So that was the right thing to do,[br]I think, and took that DMA. I'm actually
0:45:26.299,0:45:29.299
converse on this. I thought this was crap.[br]And actually, I think this was a really
0:45:29.299,0:45:33.319
good example of balanced design. What's[br]the right tool for the job? Software is
0:45:33.319,0:45:38.009
going to do the IO, so let's make sure[br]that the FIQ mode, it makes sure that
0:45:38.009,0:45:44.640
there's low overhead as possible. Have you[br]talked about system partitioning the MMU ?
0:45:44.640,0:45:49.569
I've seen ones about. I still think it's[br]weird and backward. I think there is a
0:45:49.569,0:45:56.029
strong argument though that a more[br]familiar TB(?) is a massively complicated
0:45:56.029,0:45:59.339
compared to what they did here. And I[br]think the main drive here was not just
0:45:59.339,0:46:06.770
area on the chip, but also to make it much[br]simpler to implement. So it worked. And I
0:46:06.770,0:46:09.450
think this was they really didn't have[br]that many shots of doing this. This wasn't
0:46:09.450,0:46:14.779
a company or a team that could afford to[br]have many goes at this product. And I
0:46:14.779,0:46:20.660
think that says it all. I think they did a[br]great job. Okay. So the ARX story is a
0:46:20.660,0:46:24.599
little bit more complicated. Remember,[br]it's gonna be this office automation
0:46:24.599,0:46:28.920
machine a bit like a Xerox star. Was going[br]to have this wonderful highres mono mode
0:46:28.920,0:46:33.729
and people gonna be laser printing from[br]it. So just like Xerox PARC Aiken started
0:46:33.729,0:46:37.911
Palo Alto based research center.[br]Californians and beanbags writing an
0:46:37.911,0:46:43.319
operating system using a micro kernel in[br]modular 2 all of the trendy boxes ticked
0:46:43.319,0:46:49.400
here for the mid 80s. It was the sounds[br]that very advanced operating system and it
0:46:49.400,0:46:54.349
did virtual memory and so on is very[br]resource hungry, though. And it was never
0:46:54.349,0:47:00.130
really very performance. Ultimately, the[br]hardware got done quicker than the
0:47:00.130,0:47:05.930
software. And after a year or two.[br]Management got the jitters. Hardware was
0:47:05.930,0:47:09.460
looming and said, well, next year we're[br]going to have the computer ready. Where's
0:47:09.460,0:47:13.650
the operating system? And the project got[br]canned. And this is a real shame. I'd love
0:47:13.650,0:47:16.599
to know more about this operating system.[br]Virtually nothing is documented outside of
0:47:16.599,0:47:21.569
ACORN. Even the people I spoke to didn't[br]work on this. A bunch of people in
0:47:21.569,0:47:25.250
California that kind of disappeared with[br]it. So if anyone has this software
0:47:25.250,0:47:29.259
archived anywhere, then get in touch.[br]Computer Museum around the corner from me
0:47:29.259,0:47:35.699
is raring to go on that. That'll be really[br]cool things to archive. So anyway, they
0:47:35.699,0:47:39.979
had now a desperate situation. They had to[br]go to Plan B, which was in under a year.
0:47:39.979,0:47:42.719
Right. An operating system for the machine[br]that was on its way to being delivered.
0:47:42.719,0:47:48.260
And it kind of shows Arthur was I mean, I[br]think the team did a really good job in
0:47:48.260,0:47:53.160
getting something out of the door in half[br]a year, but it was a little bit flaky.
0:47:53.160,0:47:57.160
Risk, cost. Then a year later, developed[br]from Arthur. I don't know if anyone's
0:47:57.160,0:48:01.609
heard of risk OS, but this is Arthur is[br]very, very niche and basically got
0:48:01.609,0:48:07.170
completely replaced by risk loss because[br]it was a bit less usable than risk.
0:48:07.170,0:48:12.059
Another really strong point that this is[br]quite a big wrong. So two megabytes going
0:48:12.059,0:48:17.400
up. So half a megabytes in the 80s going[br]up to two megabytes in the early 90s.
0:48:17.400,0:48:22.019
There's a lot of stuff in ROM. One of[br]those things is BBC Basic Five. I know
0:48:22.019,0:48:29.289
it's 2019, but I know basic is basic, but[br]BBC Basic is actually quite good. It has
0:48:29.289,0:48:32.859
procedures and it's got no support for all[br]the graphics and sound. You could give me
0:48:32.859,0:48:36.660
applications and basic and a lot of people[br]did. It's also very fast. So Sophie Wilson
0:48:36.660,0:48:42.920
wrote this this very, very optimized basic[br]interpreter. I talked about the modules
0:48:42.920,0:48:45.589
and produles (?). This is the expansion[br]room. Things are really great user
0:48:45.589,0:48:50.589
experience there. But speaking of user[br]experience, this was ARTHUR . I never used
0:48:50.589,0:48:58.559
Arthur. I just dug out from it how to play[br]with it. It is bloody horrible. So that
0:48:58.559,0:49:03.819
went away quickly. At the time also. So[br]part of this emergency plan B was to take
0:49:03.819,0:49:08.210
the ACORN soft team who were supposed to[br]be writing applications for this and get
0:49:08.210,0:49:12.079
them to quickly knock out an operating[br]system. So at launch, basically, this is
0:49:12.079,0:49:15.750
one of the only things that you could do[br]with the machine. Had a great demo called
0:49:15.750,0:49:20.569
Lender of Great Game called Arch, which is[br]3D space. You could fly around it, didn't
0:49:20.569,0:49:27.029
have business, operate serious business[br]applications. And, you know, it was very
0:49:27.029,0:49:31.079
there was not much you could do with this[br]really expensive machine at launch and
0:49:31.079,0:49:35.450
that really hurt it, I think. So let me[br]get the risk as to 1988 and this is now
0:49:35.450,0:49:42.219
looking less like a vomit sort of thing,[br]much nicer machine. And then eventually
0:49:42.219,0:49:46.749
you Risc OS 3. It was drag and drop[br]between applications. It's all
0:49:46.749,0:49:52.849
multitasking, does outline anti aliasing[br]and so on. So just lastly, I want to
0:49:52.849,0:49:55.769
quickly touch on the really interesting[br]operating systems that ACORN had a Unix
0:49:55.769,0:49:59.079
operating system. So as well as being a[br]geek, I'm also UNIX geek and I've always
0:49:59.079,0:50:04.609
been fascinated by RISCiX. These machines[br]are astonishing and expensive. They were
0:50:04.609,0:50:08.191
the existing Archimedes machines with a[br]different sticker on. So that's a 540 with
0:50:08.191,0:50:13.890
a sticker on the front. And this system[br]was developed after the Archimedes was
0:50:13.890,0:50:18.529
really designed at that point when this[br]open system was being developed. So
0:50:18.529,0:50:20.950
there's a lot of stuff about the hardware[br]that wasn't quite right for a Unix
0:50:20.950,0:50:26.230
operating system. 32K. page size on a 4[br]megabyte machine really, really killed you
0:50:26.230,0:50:29.900
in terms of your page cache and and that[br]kind of thing. They turned this into a bit
0:50:29.900,0:50:35.089
of an opportunity. At least they made good[br]on some of this. There was a quite a novel
0:50:35.089,0:50:42.380
online decompression scheme for you to[br]demand Page in all text from the binary
0:50:42.380,0:50:46.170
and it would decompressed into your search[br]to get a page, but it was stored in a
0:50:46.170,0:50:54.309
sparse way on disk. So actually on disk[br]use was a lot less than you'd expect. The
0:50:54.309,0:50:59.609
only way it fit on some of the smaller[br]machines. Also tackles the department does
0:50:59.609,0:51:05.049
on the cyber track. It turns out this is[br]their view of the 680, which is an
0:51:05.049,0:51:08.940
unreleased workstation. I love this[br]picture. I like that piece of cheese or
0:51:08.940,0:51:13.959
cake is the mouse. That's my favorite[br]part. But this is the real machine. So
0:51:13.959,0:51:20.650
this is an unreleased prototype I found at[br]the computer museum. It's notable. And
0:51:20.650,0:51:24.650
there's got to MEMC. It's got a 8MB of[br]RAM. It's only designed to run. Respects
0:51:24.650,0:51:26.099
the Unix operating system and has highres[br]monitor only doesn't have color, who's
0:51:26.099,0:51:30.279
designed to run frame maker and driver[br]laser printers and be a kind of desktop
0:51:30.279,0:51:35.249
publishing workstation. I've always been[br]fascinated by Risk X, as I said a while
0:51:35.249,0:51:41.450
ago. I hacked around on ACORN for a while.[br]I got a beating and I can. I've never seen
0:51:41.450,0:51:46.640
this before. I never used to risk X[br]machine. So there we go it Boots, it is
0:51:46.640,0:51:51.730
multi-user. But wait, there's more. It has[br]a really cool X-Server, a very fast one. I
0:51:51.730,0:51:54.730
think so. If you Wilson again worked on[br]the server here. So it's very, very well
0:51:54.730,0:51:58.019
optimized and very fast for a machine of[br]its era. And it makes quite a nice little
0:51:58.019,0:52:02.900
Unix workstation. It's quite a cool little[br]system, by the way TUDOR the guy that
0:52:02.900,0:52:07.099
designed the VIDC and the IO system called[br]me a sado forgetting this working in
0:52:07.099,0:52:14.150
there. That's my claim to fame. Finally,[br]and I want to leave some time for
0:52:14.150,0:52:19.510
questions. There's a lot of useful stuff[br]in Rome. One of them is BBC Basic Basic
0:52:19.510,0:52:23.009
has an assembler so you can walk up to[br]this machine with a floppy disk and write
0:52:23.009,0:52:30.239
assembler has a special bit of syntax[br]there and then you can just call it. And
0:52:30.239,0:52:32.460
so this is really powerful. So at school[br]or something with the floppy disk, you can
0:52:32.460,0:52:37.199
do something that's a bit more than basic[br]programing. Bizarrely, I mostly write that
0:52:37.199,0:52:41.420
with only two or three tiny syntax errors[br]after about 20 years away from this. It's
0:52:41.420,0:52:46.059
in there somewhere legacy wise. The[br]machine didn't sell very many under a
0:52:46.059,0:52:50.930
hundred thousand easily. I don't think it[br]really made a massive impact. PCs had
0:52:50.930,0:52:54.640
already taken off. By then. The ARM[br]processor is going to go on about the
0:52:54.640,0:52:58.920
company. That's that's clear that that[br]obviously has changed the world in many
0:52:58.920,0:53:04.140
ways. The thing I really took away from[br]this exercise was that a handful of smart
0:53:04.140,0:53:10.089
people. Not that many. No order of a dozen[br]designed multiple chips, designed a custom
0:53:10.089,0:53:14.869
computer from scratch, got it working. And[br]it was quite good. And I think that this
0:53:14.869,0:53:17.380
really turned people's heads. It made[br]people think differently that the people
0:53:17.380,0:53:21.160
that were not Motorola and IBM really,[br]really big companies with enormous
0:53:21.160,0:53:27.479
resources could do this and could make it[br]work. I think actually that led to the
0:53:27.479,0:53:30.809
thinking that people could design their[br]systems on the chip in the 90s and that
0:53:30.809,0:53:35.309
market taking off. So I think this is[br]really key in getting people thinking that
0:53:35.309,0:53:40.420
way. It was possible to design your own[br]silicon. And finally, I just want to thank
0:53:40.420,0:53:45.279
the people I spoke to and Adrian and[br]Jason. Their sense of computing history in
0:53:45.279,0:53:49.049
Cambridge. If you're in Cambridge, then[br]please visit there. It's a really cool
0:53:49.049,0:53:56.270
museum. And with that, I'll wrap up. If[br]there's any time for questions, then I'm
0:53:56.270,0:54:01.890
getting a blank look. No time for[br]questions. There's about 5 minutes left.
0:54:01.890,0:54:09.680
Say it or come up to me afterwards. I'm[br]happy to. Happy to talk more about this.
0:54:09.680,0:54:18.940
Applause[br]Herald:The first question is for the
0:54:18.940,0:54:29.799
Internet. Internet signal angel, will you?[br]Well, get your microphones and get the
0:54:29.799,0:54:36.700
first of the audio in the room here. Since[br]the microphone, please ask a question.
0:54:36.700,0:54:44.130
Mic1: You mentioned that the system is[br]making good use of the memory, but how is
0:54:44.130,0:54:50.459
that actually not completely being[br]installed on memory? Having no cache and
0:54:50.459,0:54:55.450
same cycle time for the cache as for the[br]memory as for the CPU.
0:54:55.450,0:55:01.140
M: Good question. So how is it not always[br]build on memory ? I mean. Well, it's
0:55:01.140,0:55:04.390
sometimes stored on memory when you do[br]something that's non sequential. You have
0:55:04.390,0:55:08.869
to take one of the slow cycles. This was[br]the N cycle. The key is this you try and
0:55:08.869,0:55:11.469
maximize the amount of time that you're[br]doing sequential stuff.
0:55:11.469,0:55:16.220
So on the ARM 2 you wanted to unroll loops[br]as much as possible. So you're fetching
0:55:16.220,0:55:19.799
your instructions sequentially, right? You[br]wanted to make as much use as lodestone
0:55:19.799,0:55:24.290
multiples. You could load single registers[br]with an individual register load, but it
0:55:24.290,0:55:28.710
was much more efficient to pay that cost.[br]Just once the start of the instruction and
0:55:28.710,0:55:33.619
then stream stuff sequentially. So you're[br]right that it is still stored sometimes,
0:55:33.619,0:55:37.141
but that was still there. Still a good[br]tradeoff, I think, for a system that
0:55:37.141,0:55:40.549
didn't have a cache for other reasons.[br]M1: Thanks.
0:55:40.549,0:55:45.530
Herald: Next question is for the Internet.[br]Signal Angel(S): Are there any other ACORN
0:55:45.530,0:55:49.839
here right now or if you want to get into[br]this kind of party together?
0:55:49.839,0:55:51.980
Herald: Can you repeat the first sentence,[br]please?
0:55:51.980,0:55:55.839
S: Sorry. The first part if you want to[br]get into this kind of popular vibe right
0:55:55.839,0:55:58.839
now.[br]M: Yeah, good question, sir. How do you
0:55:58.839,0:56:06.359
get hold of one drive prices up on eBay? I[br]guess I hate to say it might be fun to
0:56:06.359,0:56:09.170
play around and emulators. Always[br]professors that are hack around on the
0:56:09.170,0:56:12.309
real thing. Emulators always feel a bit[br]strange. There are a bunch of really good
0:56:12.309,0:56:19.180
emulators out there. Quite complete. Yeah,[br]I think it just I would just go on on on
0:56:19.180,0:56:23.260
auction sites and try and find one.[br]Unfortunately, they're not completely
0:56:23.260,0:56:27.829
rare. I mean that's that's the thing they[br]did sell. Not quite sure. Exact figure,
0:56:27.829,0:56:31.500
but you know, there were tens and tens of[br]thousands of these things made. So I would
0:56:31.500,0:56:35.130
look also in Britain more than elsewhere.[br]Although I do understand that Germany had
0:56:35.130,0:56:40.170
quite a few. If you can get a hold of one,[br]though, I do suggest doing so. I think
0:56:40.170,0:56:46.259
they're really fun to play with.[br]Herald: OK, next question.
0:56:46.259,0:56:51.860
M2: So I found myself looking at the[br]documentation for the LV MSU instructions
0:56:51.860,0:56:58.049
while devaluing something on. Just last[br]week. And just maybe wonder what's your
0:56:58.049,0:57:04.029
thought? Are there any quirks of the[br]Archimedes that have crept into the modern
0:57:04.029,0:57:06.900
arm design and instruction set that you[br]were aware of?
0:57:06.900,0:57:13.449
M: Most of them got purged. So there are[br]the 26 bits of dressing. There was a
0:57:13.449,0:57:20.039
couple of strange uses of theirs A XOR or[br]instruction into PC for changing flags. So
0:57:20.039,0:57:25.160
there was a great purge when the ARM 6 was[br]designed and the arm 6. I should know
0:57:25.160,0:57:31.559
there's ARM v3. That's what first step[br]addressing and lost this. These witnesses
0:57:31.559,0:57:35.690
got moved out.[br]I can't think of aside from just the
0:57:35.690,0:57:40.619
resulting on 32 instructions that being[br]quite quirky and having a lot of good
0:57:40.619,0:57:47.099
quirks. This shifted register as sort of a[br]free thing you can do. For example, you
0:57:47.099,0:57:52.059
can add one register to a shifted register[br]in one cycle. I think that's a good quirk.
0:57:52.059,0:57:55.119
So in terms of the inheriting that[br]instruction set and not changing those
0:57:55.119,0:58:05.959
things. Maybe that counts this.[br]Herald: Any further questions Internet ?
0:58:05.959,0:58:10.959
And if you have questions. No. Okay. No.[br]In that case, one round of applause.
0:58:10.959,0:58:12.959
M: Thank you.
0:58:12.959,0:58:13.959
Applause
0:58:13.959,0:58:14.959
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0:58:14.959,0:58:28.130
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