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Verification Toolbox

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    To provide you with additional industry perspective, we invited J L Gray from
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    Verilab. J L Gray is a consultant, and he has worked on countless projects all
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    over the world. Therefore, he brings a unique perspective. >> To this subject.
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    >> So I'm J L Gray at Verilab, vice president of North America. Verilab works
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    with semiconductor firms on the most advanced, chip development efforts, going
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    on around the world. We help build testbenches, and we also help with
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    project-planning activities. The toolbox that a verification engineer uses is
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    it's very important. There are a lot of elements in there, and many engineers
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    don't fully recognize all of the components. For example, something as simple as
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    reviewing the specification can be a tool in your toolbox. You have simulation,
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    of course. You have emulation where you actually take the design and you map it
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    in to a big massive box of hardware that behaves as if its a chip but runs a
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    little bit faster than the simulation. And you have. The ability to run an FPGA
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    prototype. Advanced stimulation is made up of several components. The first of
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    which is the most basic, which is directed tests. Effectively, you're writing a
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    scenario to map to a very specific feature of the design and you're testing to
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    make sure that, that one thing works. However, there are quite a lot of one
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    things that could be working and what you'd like to do is test A wider array of
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    things in combination. So a more advanced technique that you layer on top of the
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    directed test is called constrained random. And effectively what you do is you
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    map out the 4 problem space that you're trying to test and you, you aim your
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    simulation environment in the general direction of. ...of that, and you let it
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    randomly select, through the problem space and create its own tests that are
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    helping you to solve the problem and find the bugs. And the final piece, or a,
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    another piece you can use is, formal verification, where you're mathematically
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    proving that there are, the design is working as you expect. And you can also
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    use assertions in your design to check to make sure that as it's functioning
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    things aren't happening that are incorrect.
タイトル:
Verification Toolbox
Video Language:
English
Team:
Udacity
プロジェクト:
CS348 - Functional Hardware Verification
Duration:
02:01
Cogi-Admin added a translation

English subtitles

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