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HLD Path cs348 unit3new2

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    And here are the answers. The HDL path for the clock p port is top .in1. And
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    the HDL path for the data_p port is top.router.inout3. The HDL description of
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    hardware models can be done in different languages. And the annotation shown
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    here is the native way of showing very lock hierarchies. There is another
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    language called VHDL and it uses slashes as hierarchy delimiters. So the answer
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    on top slash in1 and top slash router slash inout 3 are also correct. In
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    general when you need to specify an HDL path in specman or
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    [UNKNOWN]
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    , please use the slash. And the tool will automatically translate to the
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    simulator according to the HDL language. To recap, a port's HDL path is the
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    concatenation of the port HDL path attribute, and the unit HDL path attribute.
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    If they are multiple units in a unit tree according to their instantiation.
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    Then those HDL paths are also concatenated. This is how you can achieve a very
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    configurable way of modeling and connecting your different components to
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    different heirachies of the HDL model.
Cím:
HLD Path cs348 unit3new2
Video Language:
English
Team:
Udacity
Projekt:
CS348 - Functional Hardware Verification
Duration:
01:21
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