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← HBUS protocol cs348 unit9

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Showing Revision 52 created 06/27/2013 by Cogi-Admin.

  1. Let's have a quick look at the basic HBUS protocol. We have the host enable
  2. signal, which indicates we have an active transfer. And then, we have the write
  3. read signal, if this is 1 we, we're having a write transfer, if it's 0 it's the
  4. read transfer. Then, we have data and address and this how a right transfer
  5. looks. Enable goes high and we apply data unto dress. The re-transfer takes two
  6. cycles again. We enable the host enables the transfer with the enable signals,
  7. and applies the address and in the second cycle the device responds with the
  8. data. We also implemented some delay so this is the delay between transfers.
  9. The HBUS also has an hsize signal. This indicates how many bytes are
  10. transferred. So here, we can see a halfword write which means 2 bytes are sent.
  11. And down here you can see a word read which means 4 bytes are read. This brings
  12. us to our next question. How many clock cycles does a halfword read transfer
  13. take? Is it 3, 4, or 5 cycles?