1 00:00:00,000 --> 00:00:18,509 35c3 pre-roll music 2 00:00:18,509 --> 00:00:25,789 Herald: The next talk is the talk on LibreSilicon project that's meant to 3 00:00:25,789 --> 00:00:31,060 create a free and open silicon manufacturing process. And our speakers 4 00:00:31,060 --> 00:00:37,220 today are leviathan, chipforge and Andreas Westerwick, creators of 5 00:00:37,220 --> 00:00:44,600 LibreSilicon. So let's give them a firm round of applause and please welcome them. 6 00:00:44,600 --> 00:00:50,000 applause 7 00:00:50,000 --> 00:01:00,079 David: Oh, it works, ok. That's problem. That's what essentially is all this fuss 8 00:01:00,079 --> 00:01:09,490 about is actually a description of how we... what this waver means and where we 9 00:01:09,490 --> 00:01:19,950 will go with it. And yeah, I give now already over to Hagen which already starts 10 00:01:19,950 --> 00:01:28,500 elaborating on the basic conceptional things. 11 00:01:28,500 --> 00:01:39,539 Hagen: OK. Hello everybody. Hope you have a fresh mind. It could be heavy. OK. Let's 12 00:01:39,539 --> 00:01:53,479 start. What we are. Last year David was involved at the project to looking for 13 00:01:53,479 --> 00:01:59,719 free silicon, just a way to manufacture his own chips and figured out it's 14 00:01:59,719 --> 00:02:05,619 difficult. You need a lot of contracts for that, NDAs (non-disclosure agreements). So 15 00:02:05,619 --> 00:02:10,090 he looked around and find a clean room. We had to come in and say, OK, we can rent 16 00:02:10,090 --> 00:02:17,010 it. Then he entered a scene on the last Congress - a lightning talk - and said, I 17 00:02:17,010 --> 00:02:24,510 like to do that. And I wasn't in the auditorium there, but a guy told me later, 18 00:02:24,510 --> 00:02:29,750 OK, look at this lightning talk. It's very interesting. You'd already doing chips. So 19 00:02:29,750 --> 00:02:37,890 I entered in sees it or seen the talk recording and see it. Nice idea, I will do 20 00:02:37,890 --> 00:02:49,320 that too. And the whole year we meet us by mumble. It's just a thing of distance you 21 00:02:49,320 --> 00:02:56,970 know. David is located in Hong Kong. The clean room is there. And I worked from 22 00:02:56,970 --> 00:03:05,560 Germany. So we exchanged e-mails. We talked on a mailing list. We built up a 23 00:03:05,560 --> 00:03:14,000 small community for that and we had a first hackathon just to figure it out, 24 00:03:14,000 --> 00:03:17,890 what we are doing with the tools, which tools are available how we can use them, 25 00:03:17,890 --> 00:03:26,800 are they usable at all or not. And this was in May and during the process the 26 00:03:26,800 --> 00:03:34,430 group wised up and already two of us got their qualification to enter the clean 27 00:03:34,430 --> 00:03:39,720 room. The Hong Kong University is a little bit strict in that. You have to sit 28 00:03:39,720 --> 00:03:46,230 there in the courses, you have to do exams and if you're fine with the exam then you 29 00:03:46,230 --> 00:03:51,620 get the permissions to go in. So Victor which is on the most left and David on 30 00:03:51,620 --> 00:03:55,930 the most right, they have the qualification for that and they 31 00:03:55,930 --> 00:04:03,010 manufacture our wafer which you have seen there. It's a small one, but it's the 32 00:04:03,010 --> 00:04:12,190 first stuff we have, right? OK. The basic points, what we are doing. We are using 33 00:04:12,190 --> 00:04:19,730 a quite, let's see, old technologies from the 80s. It's one micrometer feature size. 34 00:04:19,730 --> 00:04:26,270 It means a gate length of the transistor has one micron. It's not comparable with 35 00:04:26,270 --> 00:04:31,690 all the processors you can buy now. It's quite old, it's really stuff from the 80s. 36 00:04:31,690 --> 00:04:38,350 But we do it in a new way. We don't use the technology from the 80s. We do it with 37 00:04:38,350 --> 00:04:45,870 the knowledge and all the experience from newer technology. Doing it again and using 38 00:04:45,870 --> 00:04:52,821 some steps which are not so common, well, it wasn't common in the 80s. So why one 39 00:04:52,821 --> 00:05:02,370 micron? One micron also means that the transistors are very robust against five 40 00:05:02,370 --> 00:05:12,080 volt. Five volt was a usual supply voltage in the 80s, 90s and something like that. 41 00:05:12,080 --> 00:05:19,311 Now the supply voltage is going down, down to less than one volt but for 42 00:05:19,311 --> 00:05:27,630 tinkerers, for hobbyists, for makers, it's a nice value because older stuff, many 43 00:05:27,630 --> 00:05:36,090 boards are still working with five volts and we're able to handle this voltage. So 44 00:05:36,090 --> 00:05:44,000 we have a twin-well process; usually in the 80s there was just one well. OK, we 45 00:05:44,000 --> 00:05:50,419 have to hurry up. We have three metal layers. We have interesting additions and 46 00:05:50,419 --> 00:05:57,000 we are suitable for low tech. Ghetto tech, I would say. You can use it without 47 00:05:57,000 --> 00:06:03,410 sophisticated equipment. We can analog stuff and so on and analog stuff means you 48 00:06:03,410 --> 00:06:11,510 don't need small structures. OK. Areas where we have to work on. First, the 49 00:06:11,510 --> 00:06:18,830 process. It's almost done. You have figured out it works with measuring. OK, 50 00:06:18,830 --> 00:06:24,370 the next stuff: we need the tools. But the tools are also very old and mostly not 51 00:06:24,370 --> 00:06:30,550 usable. We have to deal with that stuff. We have to rethink the tooling for that 52 00:06:30,550 --> 00:06:38,330 and we need standard cells. That's my task. OK, so a couple of thoughts about 53 00:06:38,330 --> 00:06:45,330 standard cells. They are very common. Usually, if you have a need to translate 54 00:06:45,330 --> 00:06:54,630 your Verilog or VHDL and to bring it on a silicon you need small gates. NAND gates, 55 00:06:54,630 --> 00:07:04,731 OR gates and so on. But these gates need a lot of representation, the combinatorial 56 00:07:04,731 --> 00:07:08,680 sequencing. So OK. These are typical cells. Just a couple of them. But imagine, 57 00:07:08,680 --> 00:07:16,240 we need much much more and there's design goals for the standard cells as we need 58 00:07:16,240 --> 00:07:24,080 almost complete possibilities. If you have just this small selection of cells, the 59 00:07:24,080 --> 00:07:33,040 netlist becomes huge and every gate in the netlist also means a dedicated delay. If 60 00:07:33,040 --> 00:07:39,230 you have long chains we have a long delay so that our operating frequency goes down. 61 00:07:39,230 --> 00:07:46,030 So if you have more complex gates we are better but doing all this stuff is heavy, 62 00:07:46,030 --> 00:07:54,530 but we like to be lower power. That means our cells have to be consumption less 63 00:07:54,530 --> 00:08:00,610 power than usual. We want to be fast but yes, of course, it doesn't fit all 64 00:08:00,610 --> 00:08:07,461 together. OK. So we need it for simulation. We need it for synthesis. We 65 00:08:07,461 --> 00:08:15,470 need it for timing. As you can see everywhere on the slides and, of course, 66 00:08:15,470 --> 00:08:22,139 documentation. That's a lot of work. We are a small team. I am the only guy who is 67 00:08:22,139 --> 00:08:26,270 dealing with the standard cells it's usually our teams also are doing that. So 68 00:08:26,270 --> 00:08:33,750 OK, we need a tool for that which does all the stuff for us. And this cell generator, 69 00:08:33,750 --> 00:08:42,360 I called it popcorn, because I put in some corn and it rised up with the heat. So we 70 00:08:42,360 --> 00:08:54,310 can get all the representation. So currently I have this tool on the 71 00:08:54,310 --> 00:09:01,880 repository which is Tcl which does some stuff I like, I need, but not all. But it 72 00:09:01,880 --> 00:09:07,650 already seems very ugly. So for me I like to rewrite that but I don't figure out 73 00:09:07,650 --> 00:09:12,600 currently which language I like to use for that. Next time it could be rust, it could 74 00:09:12,600 --> 00:09:18,140 be scheme or something like that. We need another language for that. So if someone 75 00:09:18,140 --> 00:09:23,390 would help - please, but that's the next task, if you have the wafer done 76 00:09:23,390 --> 00:09:31,120 completely and measured. OK. That's a link for the repository where you can look at 77 00:09:31,120 --> 00:09:37,260 the current status and there's a wiki where I like to describe why I'm doing 78 00:09:37,260 --> 00:09:45,580 what in which way. But yes, we have to do a lot more. OK. 79 00:09:45,580 --> 00:09:54,820 Andreas: OK. Hi. I take a look at the current tooling that exists like 80 00:09:54,820 --> 00:10:02,160 layouting, place and route to minimize the yield on the wafer. And obviously because 81 00:10:02,160 --> 00:10:08,920 this is the LibreSilicon project we look at open source tools. So we have Yosys and 82 00:10:08,920 --> 00:10:16,760 graywolf, qrouter and several other FPGA routers that exist. Yosys is pretty good. 83 00:10:16,760 --> 00:10:23,790 We can probably use this for the synthesis. But the other tools, they lack 84 00:10:23,790 --> 00:10:31,450 very critical qualities for this... for silicon because they, for example, they 85 00:10:31,450 --> 00:10:40,630 are part of qflow which is an FPGA workflow. So the graywolf tool, it 86 00:10:40,630 --> 00:10:49,810 originates in academia. It's, like, it's many decades old. It comes with some very 87 00:10:49,810 --> 00:10:55,209 good ideas, for example simulated annealing which is a meta-heuristic 88 00:10:55,209 --> 00:11:01,740 you can use to solve NP-hard problems, but it's only one of the many choices you can 89 00:11:01,740 --> 00:11:10,630 make to solve the extra hard problems. But it also comes with bad implementation, for 90 00:11:10,630 --> 00:11:17,220 example inline syscalls is a very bad idea. And it's also written in C and blah 91 00:11:17,220 --> 00:11:24,950 blah, OK. Qrouter is actually... it's pretty good. It started in 2011 by Tim 92 00:11:24,950 --> 00:11:33,810 Edwards. It's widely used for, by hobbyists and enthusiasts to route for FPGAs. But 93 00:11:33,810 --> 00:11:37,890 it's not ready for silicon and it's especially not ready for our LibreSilicon 94 00:11:37,890 --> 00:11:49,250 process which would require us to to write a lot of C code for Qrouter. Also 95 00:11:49,250 --> 00:11:56,029 parallelism apparently is not in scope, so I mean if we want to scale up, for example 96 00:11:56,029 --> 00:12:04,339 place and route in the cloud or whatever or use modern CPU architectures, we are stuck 97 00:12:04,339 --> 00:12:11,690 with sequential routing which is pretty bad. Also it lacks a very important 98 00:12:11,690 --> 00:12:18,310 aspect, in my opinion, which is formal correctness. So when we produce wafers in 99 00:12:18,310 --> 00:12:25,480 the fab we want to make sure that they don't blow up in our faces. This is why we 100 00:12:25,480 --> 00:12:31,350 need some form of proof that our algorithms are correct and therefore the 101 00:12:31,350 --> 00:12:41,310 result is correct. There are also other productive tools that are proprietary 102 00:12:41,310 --> 00:12:45,220 where we can look at, but we cannot use it or fork it or whatever but we can learn 103 00:12:45,220 --> 00:12:52,290 from the research that has been done, for example BonnRoute. BonnRoute is used by 104 00:12:52,290 --> 00:13:01,330 IBM. The Cadence suite, I believe, is used by Intel and the Alliance tools is French 105 00:13:01,330 --> 00:13:08,339 academia. Very UNIXy, I mean it's a very it's a very large set of small tools that 106 00:13:08,339 --> 00:13:12,640 convert different file formats to another. I mean, maybe you encountered this problem 107 00:13:12,640 --> 00:13:17,680 before when you did some hardware design; you have many different file formats that 108 00:13:17,680 --> 00:13:24,779 all don't play together very well. So you have tools like X to Y which convert file 109 00:13:24,779 --> 00:13:33,390 format x to y. And you see when you want to place and route and layout a very very 110 00:13:33,390 --> 00:13:39,839 large chip, like a Very Large Silicon Integration, then this isn't even done, 111 00:13:39,839 --> 00:13:45,451 like, automatically by tools. This is done with manpower. When you look at a very 112 00:13:45,451 --> 00:13:54,029 large chip done by Intel or IBM. So this is an example of a very very large chip as 113 00:13:54,029 --> 00:14:02,769 you can see. I mean do you think this has been done by automation like industry 5.0? 114 00:14:02,769 --> 00:14:08,940 No. This is all manpower and a lot of manpower. Which we don't have, The 115 00:14:08,940 --> 00:14:17,180 LibreSilicon project at the moment. So this is the state of the art is like 116 00:14:17,180 --> 00:14:25,079 okay the manpower thing is one aspect but the other thing is so what you do is 117 00:14:25,079 --> 00:14:36,360 you do placing and routing at different steps at the design process so you do 118 00:14:36,360 --> 00:14:44,829 placing for a very large chip, floor planning and then you do a global routing 119 00:14:44,829 --> 00:14:51,730 which is you /can imagine it like routing along a rough chessboard. And 120 00:14:51,730 --> 00:14:55,660 after that you do a very detailed routing where all the different 121 00:14:55,660 --> 00:15:03,730 constraints regarding your technology come into play and so again the formal 122 00:15:03,730 --> 00:15:09,920 correctness aspect. So you have some imperative algorithm that you cannot prove 123 00:15:09,920 --> 00:15:16,100 will blow up. And it's also not a very parallel code. So you're still stuck with 124 00:15:16,100 --> 00:15:28,810 the sequential nature of the code and you have no parallelism. What we propose is to 125 00:15:28,810 --> 00:15:35,149 not place and route for large chip but to decompose the large chip into much 126 00:15:35,149 --> 00:15:42,779 smaller units like a component hierarchy or a sub cell hierarchy and then place and 127 00:15:42,779 --> 00:15:50,550 route the small chips at the same time and then reuse the small units in larger 128 00:15:50,550 --> 00:15:57,540 units. So you get an evaluation tree you can work on and compile just the 129 00:15:57,540 --> 00:16:09,680 components you need. Also we propose satisfiability modulo theory solvers so we 130 00:16:09,680 --> 00:16:17,850 can have some first order logic where we can have constraints on the components, 131 00:16:17,850 --> 00:16:24,089 how they are placed for example they don't - they must not overlap. 132 00:16:24,089 --> 00:16:32,680 Let's take the most simple example I will show you like later. And also we want to 133 00:16:32,680 --> 00:16:44,110 achieve parallel or declarative code. So as you can see we have some, we have many 134 00:16:44,110 --> 00:16:50,630 disagreements with academia and industry which work very well together for example 135 00:16:50,630 --> 00:16:56,420 when you want to study semiconductor design you have to sign some NDAs with IBM 136 00:16:56,420 --> 00:17:05,699 or Intel to do that. So, they say placement and routing or floor planning 137 00:17:05,699 --> 00:17:11,010 and routing are different problems and they need to be solved at different times 138 00:17:11,010 --> 00:17:18,589 in the process. And then all the components can be registers or NAND gates 139 00:17:18,589 --> 00:17:23,150 it does matter they all treated the same. No it only matters that uh the floor 140 00:17:23,150 --> 00:17:27,079 planning stand first and then the routing the closed routing then a detailed 141 00:17:27,079 --> 00:17:34,919 routing. What we propose is that place and route is actually the same problem and 142 00:17:34,919 --> 00:17:45,350 that registers are different from full adders. Okay. So the geographical 143 00:17:45,350 --> 00:17:53,720 partitioning of a wafer is called floor planning or the placing step. And this 144 00:17:53,720 --> 00:18:00,910 results in a cut tree. So this is how they do routing hierarchies. They just divide 145 00:18:00,910 --> 00:18:08,670 the wafer into smaller pieces and then do the following steps based on this 146 00:18:08,670 --> 00:18:16,250 placement. What we want to do is have subcell hierarchies and those sub cells 147 00:18:16,250 --> 00:18:23,230 they are either explicit like they are explicitly developed for example the 148 00:18:23,230 --> 00:18:32,559 rocket ship is very modular and it has many explicit verilog modules you can use 149 00:18:32,559 --> 00:18:39,700 and place and route that and then reuse it. And it also has implicit sub cells like 150 00:18:39,700 --> 00:18:45,780 for example most of the time. For example you have a full adder it obviously is 151 00:18:45,780 --> 00:18:52,190 composed of one bit adders so you can place and route one bit adder and then 152 00:18:52,190 --> 00:18:56,840 place and route based on the one bit adders that you artfully placed and routed. 153 00:18:56,840 --> 00:19:00,760 And as a result you get a full adder. That's just one example but I will show 154 00:19:00,760 --> 00:19:11,370 you a tree, a few slides. So there you see parallelism. There's something very 155 00:19:11,370 --> 00:19:19,990 important for us. BonnRoute allocates a lot of research to have some mathematical 156 00:19:19,990 --> 00:19:27,760 model for concurrency and shared memory models. qrouter, which is the open source 157 00:19:27,760 --> 00:19:34,670 alternative, has none. I mean that's apparently not in scope. And what I 158 00:19:34,670 --> 00:19:46,559 propose for the LibreSilicon compiler is the map and reduce approach. And as I've 159 00:19:46,559 --> 00:19:52,130 mentioned you get explicit subcell hierarchies through high modularization. 160 00:19:52,130 --> 00:19:56,620 That is done by the developers and you also get implicit subcell hierarchies 161 00:19:56,620 --> 00:20:05,860 by compression-like algorithms that exline as opposed to inline the registers or one 162 00:20:05,860 --> 00:20:13,900 bit adders. And this is also about preserving these newfound hierarchies in 163 00:20:13,900 --> 00:20:20,100 the compiler interfaces so you don't end up inlining them again because this is 164 00:20:20,100 --> 00:20:24,640 not a Von Neumann architecture where it would make sense to inline a lot of code. 165 00:20:24,640 --> 00:20:30,640 So the code runs on the stack and the level 1 cache. This is about reusing 166 00:20:30,640 --> 00:20:42,230 components. Okay. So this is a part of the rocket ship, the system bus is one 167 00:20:42,230 --> 00:20:50,200 component of a very modular chip rocket ship. And as you can see it is composed of 168 00:20:50,200 --> 00:20:56,980 several simple lazy modules and those simple modules are again composed of other 169 00:20:56,980 --> 00:21:01,530 components. And then you have a lot of queues and this number on the left says 170 00:21:01,530 --> 00:21:08,039 how many times it's been used. For example queue 15 is used 5 times in the 171 00:21:08,039 --> 00:21:16,400 AXI4Deinterleaver and this is only the explicit hierarchy that is declared by the 172 00:21:16,400 --> 00:21:23,730 developer. Okay. Now when you apply some compression-like algorithms you can 173 00:21:23,730 --> 00:21:32,090 actually gain, you can get more leaves so you can be even more modular. For example 174 00:21:32,090 --> 00:21:39,549 queue 1 is composed of several implicit modules and you can see one queue is even 175 00:21:39,549 --> 00:21:46,669 reused seven times. So you just route, place and route these green leaves like 176 00:21:46,669 --> 00:21:51,760 once and then you can reuse it in the queue 1 and everywhere where queue 1 is 177 00:21:51,760 --> 00:22:02,299 reused some at some other point in the chip. Now I want to state a very simple 178 00:22:02,299 --> 00:22:10,270 optimization problem. What we need for the process is to have components and 179 00:22:10,270 --> 00:22:16,179 wires that connect the components or nets and these nets and components are actually 180 00:22:16,179 --> 00:22:24,200 rectilinear geometries, the components shall not overlap and the nets shall 181 00:22:24,200 --> 00:22:32,010 overlap with the respective pins they are supposed to connect. The minimizing goals 182 00:22:32,010 --> 00:22:36,470 of this optimization problem is layout area, which is the most critical one 183 00:22:36,470 --> 00:22:43,060 because this is what maximizes yield, the maximum wire length because it's about 184 00:22:43,060 --> 00:22:49,750 resistance, the wire count you want to keep very small but you want to allow for 185 00:22:49,750 --> 00:22:56,799 wires. The crossing number is a computational thing. It doesn't really 186 00:22:56,799 --> 00:23:01,460 matter for the implementation on the silicon and you also want maybe you want 187 00:23:01,460 --> 00:23:11,850 to minimize the wire jogs which is bends in the wire. So to to solve optimization 188 00:23:11,850 --> 00:23:19,309 problems in 2018 maybe you want to use an abstraction from the SAT solvers. You used 189 00:23:19,309 --> 00:23:25,780 to know academia came up with some pretty neat theory is called satisfiability 190 00:23:25,780 --> 00:23:35,220 modulo theories and you can just put some first order logic and give it to a solver. 191 00:23:35,220 --> 00:23:41,370 I've listed a few. For example ABC is used by Yosys and Z3 from Microsoft, also very 192 00:23:41,370 --> 00:23:46,780 promising product, but you can obviously choose from many products by academia and 193 00:23:46,780 --> 00:23:54,559 industry. Just a quick reminder what boolean satisfiability is: find 194 00:23:54,559 --> 00:24:00,250 assignments for all these six variables which are boolean so that the whole term 195 00:24:00,250 --> 00:24:06,650 is true. And now with SMT or satisfiability modulo theories you can do 196 00:24:06,650 --> 00:24:13,770 the same thing but now with integers and also more complex data types but integers 197 00:24:13,770 --> 00:24:22,950 are the most interesting. So let's do something with SMT. For example we have a 198 00:24:22,950 --> 00:24:29,280 component that is rectangular. And now you can see this is like a Cartesian 199 00:24:29,280 --> 00:24:35,260 coordinate system and you have the left bottom point which is x and y and then you 200 00:24:35,260 --> 00:24:41,320 have the right and the top point. And now if you for example have this problem that 201 00:24:41,320 --> 00:24:47,070 you don't want to have overlapping rectangles you can have a rectangle A and 202 00:24:47,070 --> 00:24:57,470 rectangle B and declare these coordinates and then have some proposition that shall 203 00:24:57,470 --> 00:25:04,290 be true and to have a proposition that says they shall not overlap is to say 204 00:25:04,290 --> 00:25:10,340 this. I mean it's actually the lower half that makes sure that they don't overlap 205 00:25:10,340 --> 00:25:15,200 and the upper half makes sure that the components actually have the right 206 00:25:15,200 --> 00:25:19,860 dimensions. Well in this example they obviously have the same dimensions the 207 00:25:19,860 --> 00:25:26,360 same components. And so you make sure that the left point of the second 208 00:25:26,360 --> 00:25:44,370 rectangle is right of the... Okay no, never mind. One last important point I 209 00:25:44,370 --> 00:25:50,370 want to make is that this this framework we want to create, it's not based on the 210 00:25:50,370 --> 00:25:57,760 inheritance model that we've seen in the process steps right now. But we want to 211 00:25:57,760 --> 00:26:02,169 combine the problems. For example the overlapping problem, the pin connect 212 00:26:02,169 --> 00:26:05,360 problem, and then arbitrary constraints that come up during the process 213 00:26:05,360 --> 00:26:10,330 development that Dave and Hagen will supply me with and I will formulate that 214 00:26:10,330 --> 00:26:15,390 in first order logic. And then this makes sure it's formally correct and it 215 00:26:15,390 --> 00:26:24,149 doesn't blow up. And as you can tell I mean I've combined many NP-hard 216 00:26:24,149 --> 00:26:29,480 problems at the same time but I think we can manage that if we have very small 217 00:26:29,480 --> 00:26:37,419 cells so I'd suggest we just stay here and don't do all this for very large chips but 218 00:26:37,419 --> 00:26:45,840 reuse small chips and then reuse the small chips in other small chips. The silicon 219 00:26:45,840 --> 00:26:54,500 compiler is one half of maximizing yields. And the other half is to get the 220 00:26:54,500 --> 00:27:03,260 process right so to get the process right, we have David and Victor. So please. 221 00:27:03,260 --> 00:27:14,030 David: So thanks for the handover. So very first. There's a lot of questions why Hong 222 00:27:14,030 --> 00:27:19,539 Kong. So one thing why this is a really suitable place to do that is 223 00:27:19,539 --> 00:27:27,490 because of history like the epic Commodore 64 has been made in Hong Kong. Then the 224 00:27:27,490 --> 00:27:32,600 chips in the first Macintosh have been made in Hong Kong and all of these 225 00:27:32,600 --> 00:27:42,549 manufacturing lines. Some of them at least one is still available. So also there is a 226 00:27:42,549 --> 00:27:51,250 very advanced laboratory. That's the NFF, Nano Fabrication Facility in 227 00:27:51,250 --> 00:27:59,309 Clearwater Bay and they let us kindly use their equipment to develop this process. 228 00:27:59,309 --> 00:28:07,140 Also one of the sectors I mentioned before, RCL semiconductors, they're really 229 00:28:07,140 --> 00:28:12,270 open to introduce LibreSilicon in their mass-manufacturing lines: one in Shenzen, 230 00:28:12,270 --> 00:28:28,470 one in Tai Po. So in conclusion of that we have advanced R&D labs there. There is 231 00:28:28,470 --> 00:28:35,770 factories available. We can easily export it to here over channels which already 232 00:28:35,770 --> 00:28:43,840 exist. Right. And also in general it's just more relaxed over there. And I don't 233 00:28:43,840 --> 00:28:59,179 like minus degrees. So our process is a little bit of a monster. So it makes sense 234 00:28:59,179 --> 00:29:05,460 to tackle that one by one so we are right now feeling ourselves upwards to get the 235 00:29:05,460 --> 00:29:14,000 standard CMOS debugged, final with optimized frequencies there. But we 236 00:29:14,000 --> 00:29:19,210 already have on the Pearl River, I've shown you, we already have test structures for 237 00:29:19,210 --> 00:29:27,439 high voltage MOSFETS, B junction transistors, Zener diodes, even flash, 238 00:29:27,439 --> 00:29:35,010 resistors, and caps. So it's only a question of effort I guess in the next few 239 00:29:35,010 --> 00:29:45,620 months to get that working. When we designed the process like, how it usually 240 00:29:45,620 --> 00:29:50,750 works when you make a process, you look at the machines you have availlable, what can 241 00:29:50,750 --> 00:29:57,089 these machines do, optimum operation range and then you look what substrate, what 242 00:29:57,089 --> 00:30:01,220 material you have available and then you start tinkering you own little proprietary 243 00:30:01,220 --> 00:30:08,731 process. That's how fabs do that. And we said, OK, well, to the point where we look 244 00:30:08,731 --> 00:30:15,760 at the machines - what can they do? We do the same, but afterwards we look that 245 00:30:15,760 --> 00:30:23,950 it's portable. Not specific to the equipment. So just because we have certain 246 00:30:23,950 --> 00:30:29,610 machines which can do awesome things, but are really exotic, doesn't mean we have to 247 00:30:29,610 --> 00:30:37,690 use them. So we avoid exalting machines so that it's as portable as possible. And we 248 00:30:37,690 --> 00:30:43,180 also try to use wet etching whenever possible in order to make sure that you 249 00:30:43,180 --> 00:30:55,110 even can build it in a basement. And here Evan Heisenberg may be interested now in, 250 00:30:55,110 --> 00:31:02,610 you know, changing business into a less dangerous business. And, yeah, they can't 251 00:31:02,610 --> 00:31:06,990 be leading the innovation hub Hamburg I've seen, like this improvised clean room with 252 00:31:06,990 --> 00:31:15,920 just a diffusion furnace. So, that's a cross-section of the... it's not 253 00:31:15,920 --> 00:31:21,539 finalised, but you see a cross section theoretical that's... by the way, you can 254 00:31:21,539 --> 00:31:28,710 find it on GitHub as well. It's all in the publications, everything we develop, all 255 00:31:28,710 --> 00:31:37,830 the measurement data, all this on GitHub. So that's actually the layout of these 256 00:31:37,830 --> 00:31:48,260 little squares here on the wafer. You see the apple in the middle. It's just in 257 00:31:48,260 --> 00:31:55,929 this year. That's, uh, it's nice. I have a Python script in the GDS2 generator 258 00:31:55,929 --> 00:32:01,289 tool folder for Python and you can take any png or anything and just 259 00:32:01,289 --> 00:32:06,750 convert it into layout format, so you can put your own pictures onto the metal free 260 00:32:06,750 --> 00:32:14,771 layer. So in case you already have interest into making little trips also. 261 00:32:14,771 --> 00:32:20,570 It's also possible to make, like, ear rings also with ... We don't care as long 262 00:32:20,570 --> 00:32:26,580 as there are 4 more millimeters on the silicon. You can put pictures on the 263 00:32:26,580 --> 00:32:36,670 silicon. So that was the Pearl River right. And the Pearl River fulfills the 264 00:32:36,670 --> 00:32:44,620 function for us at the moment to debug all the features of this LibreSilicon process. 265 00:32:44,620 --> 00:32:50,651 Then the next thing we have to use it to calibrate new foundries so now, we 266 00:32:50,651 --> 00:32:56,250 developed it at the NFF in Clearwater Bay right. And afterwards we go over to HQ 267 00:32:56,250 --> 00:33:03,130 with, to the RCL guys in Tai Po, and they have the machines and then we have to pipe 268 00:33:03,130 --> 00:33:08,640 the Pearl River layout through there as well and repeat that process over and over 269 00:33:08,640 --> 00:33:15,410 again until the measurement data, like the frequent, the you know the Beta 270 00:33:15,410 --> 00:33:21,860 depending on Omega of the transistors and the resistance of the wires and everything 271 00:33:21,860 --> 00:33:28,340 kind of is the same as at NFF so that you can basically, as I mentioned before one 272 00:33:28,340 --> 00:33:32,870 of the design concerns is portability that you can basically prototype a chip 273 00:33:32,870 --> 00:33:39,860 at the NFF and then produce it in RCL or in maybe some other fab in Shenzhen or 274 00:33:39,860 --> 00:33:48,840 whatever. And so and if there are new features coming out which also make a new 275 00:33:48,840 --> 00:33:59,990 release of the Pearl River test waver and we give that around they push it to GitHub 276 00:33:59,990 --> 00:34:09,049 and people can introduce and calibrate the process to support the new feature. And so 277 00:34:09,049 --> 00:34:13,159 that's how does that work. So usually, typically you have something like a photo 278 00:34:13,159 --> 00:34:19,809 mask like here. I didn't bring that one because it's in a clean room there and the 279 00:34:19,809 --> 00:34:26,819 dust might scratch my micro structures on there. So also afterwards I have to clean 280 00:34:26,819 --> 00:34:31,569 it for half an hour and when I come back to Hong Kong from here I'm so jetlagged I 281 00:34:31,569 --> 00:34:35,492 just want to get started again, not wait for the mask. 282 00:34:35,492 --> 00:34:41,219 But there's a picture. And these masks, 283 00:34:41,219 --> 00:34:49,359 usually a stepper/aligner specific. If you don't have a stepper then you need to make 284 00:34:49,359 --> 00:34:56,229 a direct transfer that means you actually have to put the chips in the size you 285 00:34:56,229 --> 00:35:00,459 want to expose them directly onto the mask. Then press the mask onto the 286 00:35:00,459 --> 00:35:05,510 photoresist, expose and develop. That's messy because you have to clean the mask 287 00:35:05,510 --> 00:35:10,499 all the time. And it really depends. So actually you can do exposure even without 288 00:35:10,499 --> 00:35:15,029 a stepper. So we actually really could do it also there in this university lab in 289 00:35:15,029 --> 00:35:24,440 Hamburg. So all you need is a new UV light. laugs So we have a little bit more 290 00:35:24,440 --> 00:35:33,019 advanced tech in Hong Kong. So we have here an SVG coater, this baby dispenses 291 00:35:33,019 --> 00:35:40,630 automatically HPR 504, a resist. So we actually just have to put in the left, you 292 00:35:40,630 --> 00:35:45,589 see the cassette slot. So you put there like twenty five wavers or so and then you 293 00:35:45,589 --> 00:35:51,390 have a receive slot and put another cassette there and it just starts sucking 294 00:35:51,390 --> 00:36:01,640 in the wafers one by one, puts primer on it, soft bakes it, and easy. Then you 295 00:36:01,640 --> 00:36:09,859 expose it, develop it, hard bake it, chilled. We have two types of resist actually 296 00:36:09,859 --> 00:36:19,039 and the 6400L for the implantation unfortunately has to be put in manually. 297 00:36:19,039 --> 00:36:24,119 So it comes and it gives you 10 seconds to open the chamber and put the resist on 298 00:36:24,119 --> 00:36:31,469 it. In both cases however it doesn't really matter so much because the 299 00:36:31,469 --> 00:36:37,779 thickness of the resist is depending on the RPMs of the spin coating unit. So you 300 00:36:37,779 --> 00:36:45,269 just have to kind of put two thirds of the waver should be somehow covered with the 301 00:36:45,269 --> 00:36:54,190 resist and the excess resist goes away. But you have to control the RPMs because 302 00:36:54,190 --> 00:37:03,219 depending on when you do wet etching for instance and HPR 504 has to be enough 303 00:37:03,219 --> 00:37:11,059 thick because of selectivity, so that you don't etch and consume the polymer, 304 00:37:11,059 --> 00:37:14,760 the resist. So you have to make it thick enough that you don't have, 305 00:37:14,760 --> 00:37:17,590 you haven't consumed all the polymer before 306 00:37:17,590 --> 00:37:23,740 you have etched your structures. And the same goes for the implantation because you 307 00:37:23,740 --> 00:37:41,710 need 6400L, this one can sustain higher temperatures so you can use an implanter. 308 00:37:41,710 --> 00:37:48,950 Now afterwards after exposure development it looks like that. That's an alignment 309 00:37:48,950 --> 00:37:57,079 cross for our optical stepper and for instance that's our ring oscillator. So 310 00:37:57,079 --> 00:38:07,020 it's one of the structures on our Pearl River actually. So N well, P well. I have 311 00:38:07,020 --> 00:38:11,500 to hurry up, only 10 minutes or so. So that's a picture of the developing we have 312 00:38:11,500 --> 00:38:16,269 some P well mask developed so we have everywhere resist except in this little 313 00:38:16,269 --> 00:38:22,739 crosses and stripes there. That's there below is the silicon where we implant. The 314 00:38:22,739 --> 00:38:32,789 recipe is easy, first coat, expose the implant and then resist strip. Same for 315 00:38:32,789 --> 00:38:41,480 the P well and after the resist strip you can put it into a diffusion furnace in 316 00:38:41,480 --> 00:38:48,809 the atmosphere for like four hours. So where does the four hours come from? So 317 00:38:48,809 --> 00:38:54,190 we have the Fick's equation. And the Fick's equation is essentially in a 318 00:38:54,190 --> 00:39:00,760 similar shape like the laplace heat conduction equation, so to solve, there 319 00:39:00,760 --> 00:39:07,079 are already nice solutions for it. So for instance if you use boron or phosphorus 320 00:39:07,079 --> 00:39:13,200 which has the nice property that they have the same constants for this Dₑ. So if you 321 00:39:13,200 --> 00:39:18,859 have the same temperature you basically have the same Dₑ for phosphorus and boron 322 00:39:18,859 --> 00:39:23,770 so you can implant them next to each other and then put them at once into the 323 00:39:23,770 --> 00:39:29,690 diffusion furnace and the wells are the same depth. So that's why these two 324 00:39:29,690 --> 00:39:36,630 materials are usually used for diffusion. So that's one of the solutions that you 325 00:39:36,630 --> 00:39:44,670 get, the surface for doping for the threshold equation which I also will rush 326 00:39:44,670 --> 00:39:53,150 through in a moment as well. The equations you see here with background 327 00:39:53,150 --> 00:40:02,080 doping it's a little bit much. As you have here this natural logarithm inside. But 328 00:40:02,080 --> 00:40:07,539 besides that you see this jump and that's how you essentially build a well, you have 329 00:40:07,539 --> 00:40:13,609 the background doping and you compensate the donors and acceptors with each other 330 00:40:13,609 --> 00:40:22,359 so that's what this absolute value of the difference means. So the threshold 331 00:40:22,359 --> 00:40:27,789 equation is pretty easy. And like basically mirrored for PMOS and NMOS that 332 00:40:27,789 --> 00:40:33,039 just like mirrored in the sense that one of the transistors as PMOS is built on a N 333 00:40:33,039 --> 00:40:47,069 well and NMOS is built on a P well. Right. And what essentially controls the 334 00:40:47,069 --> 00:40:50,930 threshold voltage, so the operational voltage, which usually in the standard 335 00:40:50,930 --> 00:40:59,400 CMOS is around 0.8 respectively minus 0.8. That's doping here like the donars 336 00:40:59,400 --> 00:41:07,709 respectively acceptors and the q as usually that's the oxide charge. This is 337 00:41:07,709 --> 00:41:16,069 usually a process specific constant but that can change. And then you get 338 00:41:16,069 --> 00:41:21,709 flash, it can change Q_SS and then it's flash. That's what you use in SONOS 339 00:41:21,709 --> 00:41:29,469 flash, stands for silicon oxide nitride oxide silicon. So there you have a 340 00:41:29,469 --> 00:41:38,680 standard again, NMOS in this case but you have a sandwich instead of a normal oxide 341 00:41:38,680 --> 00:41:44,559 layer and for the gate oxide you have a nitride and oxide. These oxide layers 342 00:41:44,559 --> 00:41:53,329 above and below the nitrate are called tunnel oxides. And the trick is that with 343 00:41:53,329 --> 00:41:58,959 high enough energy you tunnel electrons into the, through the oxide into the 344 00:41:58,959 --> 00:42:04,099 nitride where it's trapped and then you shift the operation voltage, the threshold 345 00:42:04,099 --> 00:42:11,670 of the transistor. And when you then put one at it it doesn't turn on anymore and 346 00:42:11,670 --> 00:42:18,999 that's essentially how the most used flash solution besides normal floating gate 347 00:42:18,999 --> 00:42:27,759 works. It's really simple. So. And after you get your wells out of the furnace, so 348 00:42:27,759 --> 00:42:36,109 I did a little detour. You want to make sure that the lateral diodes which got 349 00:42:36,109 --> 00:42:41,440 into existence after diffusion don't create unwanted short circuits. So we use 350 00:42:41,440 --> 00:42:46,549 the technology actually developed much later after one micron already has been 351 00:42:46,549 --> 00:42:52,559 out. It's called STI shallow trench isolation. It's from the ULSI technology 352 00:42:52,559 --> 00:42:59,019 as well as the silicide we use to reduce the resistance of the polysilicate. 353 00:42:59,019 --> 00:43:09,319 Here are some pictures, we did etch this one in the lab. That's the islands so that 354 00:43:09,319 --> 00:43:14,160 around everything going down that's the trenches in between the gates and between 355 00:43:14,160 --> 00:43:23,500 the wells. So we isolate them from each other. So the recipe is pretty easy. 356 00:43:23,500 --> 00:43:26,729 So either you have a plasma etcher around or if you're not 357 00:43:26,729 --> 00:43:31,640 rich and don't have money to buy a plasma etcher from eBay you can also get this 358 00:43:31,640 --> 00:43:43,339 tetramethylammonium hydroxide. And it's not even the german name, so cool, and 359 00:43:43,339 --> 00:43:52,369 dilute it with deionized water 3:1 and this 25% TMAH solution you heat 360 00:43:52,369 --> 00:43:57,780 it up to 80°C, dip your wafer in for six minutes and then you 361 00:43:57,780 --> 00:44:05,440 would get your structures. Metal is easier. So we did here the metal 362 00:44:05,440 --> 00:44:12,309 interconnect for the ring oscillator. They're etching it, also you make a 363 00:44:12,309 --> 00:44:18,809 vacuum, deposit 100 nanometres aluminum, 30 nanometers titanium for passivation. 364 00:44:18,809 --> 00:44:23,589 Take the vacuum away dip it into HF until you don't see streaks on the titanium, 365 00:44:23,589 --> 00:44:28,250 then into aluminum etchant until you don't see streaks from the aluminum. And then 366 00:44:28,250 --> 00:44:35,589 you have your wires. I'll skip that one. That's just really interconnect. 367 00:44:35,589 --> 00:44:44,640 But I plan to make videos soon where I go through the you know like daily video blog 368 00:44:44,640 --> 00:44:49,539 of results but just that you see that you see the oxide depending on the angle it 369 00:44:49,539 --> 00:44:57,630 has different colors. So that's L2 the isolation. And then you see the 370 00:44:57,630 --> 00:45:04,019 topological measurement device. You see this one micron because we only deposited 371 00:45:04,019 --> 00:45:12,709 a micron for now. You'll see the heights the differences and we see that one micron 372 00:45:12,709 --> 00:45:17,719 is not enough. So we'd still have these sharp edges which we don't want. So we have 373 00:45:17,719 --> 00:45:23,959 back in Hong Kong have to deposit another 2 microns. And if you want a follow up you 374 00:45:23,959 --> 00:45:31,479 go to my Github. OK? So Victor that's him and I have done that so far. It's only 375 00:45:31,479 --> 00:45:36,699 like two weeks because it took a lot of time to get all the masks manufactured and 376 00:45:36,699 --> 00:45:41,789 so a lot of bureaucracy. We already have that much and just stay tuned. We already 377 00:45:41,789 --> 00:45:46,819 have figured out so much in the last two weeks that it shouldn't be long before we 378 00:45:46,819 --> 00:45:57,779 can well finish all the features of Pearl River. Create models with Hawkins popcorn 379 00:45:57,779 --> 00:46:02,640 and start figuring out all the analog stuff for our MCU and then we make 380 00:46:02,640 --> 00:46:07,219 an MCU. That's the first thing we want to do as soon as we have the features figured 381 00:46:07,219 --> 00:46:17,409 out of Pearl River. If the Goddess is nice to us. Yeah it's a discordia figurine, 382 00:46:17,409 --> 00:46:23,319 it's really cheap on ebay. laugs So yeah. And that's like an overall 383 00:46:23,319 --> 00:46:30,700 of the features. And we want them build this microcontroller, and yes because all 384 00:46:30,700 --> 00:46:34,279 the folks don't believe that there are people who want to buy such items you 385 00:46:34,279 --> 00:46:45,319 please fill out the survey. That one is from Hagens trip, i skipped it but 386 00:46:45,319 --> 00:46:50,380 yeah. So yeah. Thanks. I'm done. And too late but sorry. 387 00:46:50,380 --> 00:47:00,900 applause 388 00:47:00,900 --> 00:47:05,770 Herald: Thank you for the talk. No, but if you wait we have time for questions. So 389 00:47:05,770 --> 00:47:10,770 there are two microphones. One is in the middle and one is on the left side of the 390 00:47:10,770 --> 00:47:16,410 stage. Line up and we're going to take some questions and there is already one 391 00:47:16,410 --> 00:47:23,269 question from Microphone number two. Microphone 2: OK. So thank you for that 392 00:47:23,269 --> 00:47:28,700 interesting talk and all the development that you're doing. I was wondering have 393 00:47:28,700 --> 00:47:37,900 you had any time to test your transistors yet. And then later on do you plan to 394 00:47:37,900 --> 00:47:42,852 release some sort of analog simulation capabilities. 395 00:47:42,852 --> 00:47:48,709 David: Yes. Thats the plan for the next few weeks after I'm back in Hongkong. We 396 00:47:48,709 --> 00:47:53,329 did go back to the cleanroom. We actually wanted to provide already something for the 397 00:47:53,329 --> 00:48:00,669 Congress. Unfortunately we were noticed, short noticed that Thursday and Friday 398 00:48:00,669 --> 00:48:06,289 they take the wet stations and the machines offline for maintenance of the 399 00:48:06,289 --> 00:48:13,140 AC. So we have already like, the wafer, we have the isolation oxides but we didn't 400 00:48:13,140 --> 00:48:19,119 have any time left to actually test the the you know only having polysilicon is 401 00:48:19,119 --> 00:48:22,730 not enough. You have to also have metal to go with probes there, that stuff is 402 00:48:22,730 --> 00:48:27,279 micron size. Hagen: Okay. So your question as I 403 00:48:27,279 --> 00:48:31,730 understand was in the direction of simulation right? We like to measure all 404 00:48:31,730 --> 00:48:38,279 the structures we have to produce and with the values we get we like to feed in spice 405 00:48:38,279 --> 00:48:45,789 models. So you can do analog simulations. And yes we like to use this technology for 406 00:48:45,789 --> 00:48:50,369 analog stuff because as I already mentioned one micron size is enough for 407 00:48:50,369 --> 00:48:56,279 analog. You don't need smaller structures. Analog all this having huge transistor 408 00:48:56,279 --> 00:49:03,849 size from 20 or 50 Microns. So they are huge, you don't need this small 409 00:49:03,849 --> 00:49:11,349 technology. So they are quite feasible for analog stuff but let's say in this way if 410 00:49:11,349 --> 00:49:16,150 you're doing analog stuff in a conventional way you have to sign all the 411 00:49:16,150 --> 00:49:21,259 NDAs and you're stuck on this technology you're using. You can't transfer your 412 00:49:21,259 --> 00:49:27,170 design to the next fab because in the next fab the PDKs are different. You have to 413 00:49:27,170 --> 00:49:31,380 transfer or to translate all the structures there for a rebuild again for 414 00:49:31,380 --> 00:49:36,250 the new technology if you have a technology which you can take from one fab 415 00:49:36,250 --> 00:49:42,720 to another like our one. You are quite happy because the analog stuff you 416 00:49:42,720 --> 00:49:49,400 designed once also fits for the next fab. So yes of course we like to support analog 417 00:49:49,400 --> 00:49:54,529 stuff. We need help for that of course we have to measure, we are currently 418 00:49:54,529 --> 00:49:58,150 developing the wafer, we are currently working on the documents how to measure, 419 00:49:58,150 --> 00:50:02,799 what we like to measure and then we have to transfer the values to spice. But we 420 00:50:02,799 --> 00:50:08,799 have documented how we are doing that. And so everyone can use the knowledge. 421 00:50:08,799 --> 00:50:12,209 Mic 2: Thank you. Herald: Thank you. Mike one please. 422 00:50:12,209 --> 00:50:17,069 Mic 1: Do you have any plans for open source mask production like. 423 00:50:17,069 --> 00:50:25,920 David: Yes. Actually the problem is only that as I mentioned before. If you want to 424 00:50:25,920 --> 00:50:30,390 have an opto mask for steppers that's always manufacturer specific. If you want 425 00:50:30,390 --> 00:50:37,529 to have a direct transfer mask not a problem. So I guess so Sam is really 426 00:50:37,529 --> 00:50:44,680 helpful in the lab. He runs the laser scriber. We could talk with the folks at 427 00:50:44,680 --> 00:50:51,499 NFF. They were really lovely helpful really. They really like to really help us 428 00:50:51,499 --> 00:50:58,959 a lot. And now that we talk with RCL. They also have laser scribers that we could 429 00:50:58,959 --> 00:51:04,660 actually also start producing masks in the long run. So yes that's certainly one of 430 00:51:04,660 --> 00:51:13,150 the things I intend to do is providing optical masks for exposure. Um yeah. 431 00:51:13,150 --> 00:51:17,180 Herald: Thank you. Uh one more question from microphone two. 432 00:51:17,180 --> 00:51:25,009 Mic 2: Great talk thanks. I'm really interested in the - what it would take to 433 00:51:25,009 --> 00:51:31,039 build the fab. What's the minimum set of tools. We've already seen a couple of 434 00:51:31,039 --> 00:51:37,559 orders of cost reduction in, through DIY bio hacking by making the tooling a lot 435 00:51:37,559 --> 00:51:44,299 cheaper. Do you see that happening within the nearest decades and your sort of work? 436 00:51:44,299 --> 00:51:51,250 David: Yes. So for instance I made my process by purpose this way that you can 437 00:51:51,250 --> 00:51:56,640 actually improvise most of it like the LTL growing and deposition and everything with 438 00:51:56,640 --> 00:52:02,390 a furnace. So what you need is a wet etcher like some wet etch station. You can 439 00:52:02,390 --> 00:52:08,200 actually there is a video from Jeri Ellsworth called "making microchips 440 00:52:08,200 --> 00:52:16,210 at home cooking with Jeri" and he does microchips in the kitchen so it's 441 00:52:16,210 --> 00:52:21,489 not, you get scared like HFS, it dissolves your bones and so on and then you see the 442 00:52:21,489 --> 00:52:25,390 guys who already have qualified, are qualified or employed there: they just 443 00:52:25,390 --> 00:52:33,739 without any PPE, nothing just grab into the HF. That's just the skill to scare 444 00:52:33,739 --> 00:52:40,509 folks from generating insurance problems. In general it's not really that dangerous 445 00:52:40,509 --> 00:52:48,069 right. You can do the stuff at home. No problem. Yeah. So we intend. So this 446 00:52:48,069 --> 00:52:55,999 process I made is so trivial. So we have also a branch called super low tech. We 447 00:52:55,999 --> 00:53:02,039 just shall essentially but it's more RnD. But you could actually help there for 448 00:53:02,039 --> 00:53:08,150 instance figure out the last details, get a furnace from eBay put it onto your 449 00:53:08,150 --> 00:53:17,410 kitchen table start RnD-ing make some git pull requests and we're super happy. Okay. 450 00:53:17,410 --> 00:53:22,109 So it's doable and the furnace you get on ebay. So no problem. 451 00:53:22,109 --> 00:53:29,559 Herald: Thank you. Microphone 1 again. Mic 1: So you just said about the 452 00:53:29,559 --> 00:53:33,660 analog stuff that a lot of that is usually under NDA from the fab. So have you 453 00:53:33,660 --> 00:53:38,509 encountered any problems with the fab and that you're currently using in that you're 454 00:53:38,509 --> 00:53:43,789 actually trying to discover these processes for yourself like you're 455 00:53:43,789 --> 00:53:48,089 generating competition that they might not like, have you had any problems with that. 456 00:53:48,089 --> 00:53:54,939 David: Oh no I had a nice phone calls, e-mails with the owner of the fab over in 457 00:53:54,939 --> 00:54:01,960 Tai Po who also has a second branch in Shenzhen that's RCL. I actually asked him 458 00:54:01,960 --> 00:54:08,109 recently "Hey is it okay when I use your logo in the presentation and implicitly 459 00:54:08,109 --> 00:54:13,319 make an advertisement for your fab here?" No prob go ahead. That is like... 460 00:54:13,319 --> 00:54:18,579 He's really eager to, LibreSilicon is what they need because every fab 461 00:54:18,579 --> 00:54:24,269 usually has to invest money in to develop it. First they develop a proprietary 462 00:54:24,269 --> 00:54:30,069 process right, or they license some proprietary process from another company 463 00:54:30,069 --> 00:54:38,260 and then they have to invest RnD costs to develop IP cores for their setup. With 464 00:54:38,260 --> 00:54:43,920 LibreSilicon the problem is solved for the companies because these foundry is 465 00:54:43,920 --> 00:54:49,099 using LibreSilicon everything the community develops is on github. And 466 00:54:49,099 --> 00:54:55,689 that's the IP catalog essentially. So they don't have to invest any 467 00:54:55,689 --> 00:55:00,380 additional money into RnD-ing IP cores that's in the nature of open source that 468 00:55:00,380 --> 00:55:05,799 there are IP cores popping into existence all the time. They can focus on the thing 469 00:55:05,799 --> 00:55:10,940 they're best at: making silicon, right? So it's actually positive but only for the 470 00:55:10,940 --> 00:55:15,579 small foundries that are really interested especially Shenzhen and now some in India 471 00:55:15,579 --> 00:55:22,420 and some of the big foundries and they will not, they are anyway the big 472 00:55:22,420 --> 00:55:27,089 companies have the tendency to be as mobile as a cargo ship. So it will take at 473 00:55:27,089 --> 00:55:32,069 least like two years until they acknowledge that LibreSilicon exists and 474 00:55:32,069 --> 00:55:39,869 then we might expect some legal you know bullying. But for now they won't even they 475 00:55:39,869 --> 00:55:46,390 just laugh right. They just laugh at best. 476 00:55:46,390 --> 00:55:49,819 Herald: We're going to have two more questions before we're out of time. 477 00:55:49,819 --> 00:55:54,459 Microphone 2. Mic 2: Why did you go for the twin well 478 00:55:54,459 --> 00:55:57,650 process as opposed to the simpler single well? 479 00:55:57,650 --> 00:56:02,180 David: Uhm that's a good point. That's also something with portability and if you 480 00:56:02,180 --> 00:56:06,769 have different events or different supplier for substrate it might be that in 481 00:56:06,769 --> 00:56:13,559 n-doped or un-doped substrate. So with twin well architecture and actually we 482 00:56:13,559 --> 00:56:18,360 have on the n-well we also built p-bases and in these n-bases, so we have actually 483 00:56:18,360 --> 00:56:27,519 like stacked wells in the n-wells and p-wells. So actually it's a one two. Um 484 00:56:27,519 --> 00:56:35,969 Pentagon Well I don't know. Um and it's just that you can shift to 485 00:56:35,969 --> 00:56:42,819 the doping of the n- and the p-substrate. According that you fit LibreSilicon 486 00:56:42,819 --> 00:56:48,259 requirements to still have the physical properties ensured by LibreSilicon. No 487 00:56:48,259 --> 00:56:53,009 matter whether you get your substrate from somewhere from Great Britain or from 488 00:56:53,009 --> 00:57:01,160 TaoBao. Hagen: Okay. The thing is we looked before 489 00:57:01,160 --> 00:57:09,349 at eBay which wafer we can get. Currently NFF is supporting us with wafers. But if 490 00:57:09,349 --> 00:57:15,239 you're looking on eBay or Alibaba. What else. We get different wafers with 491 00:57:15,239 --> 00:57:18,229 different dope agents. And if you have something with say OK 492 00:57:18,229 --> 00:57:24,599 we're just building an n-well we have to verify or lie on the p-base right, or on 493 00:57:24,599 --> 00:57:30,529 the p-substrate. And to avoid the obstacle the difficulty is: we're doing twin-wells. 494 00:57:30,529 --> 00:57:36,049 We can just regulate our own dopant inside and we are fine. We don't want to have to 495 00:57:36,049 --> 00:57:43,230 rely on the wafer or substrate itself. What was the basic point. 496 00:57:43,230 --> 00:57:46,919 Herald: Thank you. And the last question from microphone 2. 497 00:57:46,919 --> 00:57:52,319 Mic 2: So once you have your complete die how about packaging and bonding because 498 00:57:52,319 --> 00:57:56,640 if you want to use it you have to place it somehow on the PCB. 499 00:57:56,640 --> 00:58:05,140 David: Yes. So um. We have a bonding setup at Tai Po already. That's what still is 500 00:58:05,140 --> 00:58:10,199 being used at the moment in Hong Kong is to bond a packaging. Then we have some 501 00:58:10,199 --> 00:58:15,400 guys in HK SDP with packaging set up they have and can make nice tape reels and they 502 00:58:15,400 --> 00:58:21,429 have also like uh after packaging tests like: did the bonding work, is it damaged 503 00:58:21,429 --> 00:58:26,829 by the bonding, and so on. Hagen and I have figured out some nice bonding pad 504 00:58:26,829 --> 00:58:32,819 design which didn't fit at all anymore into the talk I already over talk like 505 00:58:32,819 --> 00:58:42,599 that. And but it absorbs the physical stress from bonding. So we think that 506 00:58:42,599 --> 00:58:48,359 it's aluminum covered with titanium so you don't have to sweat away any oxides right 507 00:58:48,359 --> 00:58:54,799 you have better bonding capability, better bonding properties. So it shouldn't be 508 00:58:54,799 --> 00:58:59,309 such a problem. And we have plenty of bonding and packaging labs which have 509 00:58:59,309 --> 00:59:04,819 already promised to help us. So it's really like small like to choose which one 510 00:59:04,819 --> 00:59:09,890 we take. Hagen: Just an annotation if you like a 511 00:59:09,890 --> 00:59:14,789 dedicated package please mail us. Right. We are fixed now on the dual in-line 512 00:59:14,789 --> 00:59:21,189 package. We are thinking about flip chip BGA but if you have other package which is 513 00:59:21,189 --> 00:59:25,829 more common for tinkerer or something like that please mail us. 514 00:59:25,829 --> 00:59:33,970 Herald: Thank you. Thank you for the talk. That was the talk on LibreSilicon, 515 00:59:33,970 --> 00:59:39,580 leviathan, chipforge, Andreas Westerwick and Victor. Thank you. Thank you. 516 00:59:39,580 --> 00:59:49,549 applause 517 00:59:49,549 --> 00:59:55,179 postroll music 518 00:59:55,179 --> 01:00:12,919 Subtitles created by c3subtitles.de in the year 2020. Join, and help us!